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參數(shù)資料
| 型號： | MIC2586R-2BM TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 4/22頁 |
| 文件大小： | 492K |
| 描述： | IC CTRLR/SEQ HOT SWAP 14-SOIC |
| 標準包裝： | 2,500 |
| 類型： | 熱交換控制器 |
| 應用： | 通用 |
| 內部開關： | 無 |
| 電源電壓： | 10 V ~ 80 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 14-SOIC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | MIC2586R-2BMTR MIC2586R-2BMTR-ND |
icrel, Inc.
MIC2586/MIC2586R
ecember 2012
4
M9999-122012
Pin Description (Continued)
Pin Number
Pin Name
Pin Function
4
PWRGD1
(MIC2586-1)
(MIC2586R-1)
Active-HIGH
/PWRGD1
(MIC2586-2)
(MIC2586R-2)
Active-LOW
Power-is-Good (PWRGD1 or /PWRGD1), Open-Drain Output: This pin remains deasserted during
start up while the FB pin voltage is below the V
FBH
threshold. Once the voltage at the FB pin rises
above the V
FBH
threshold, the PWRGD output asserts with minimal delay (typically d 5祍).
For the (1) options, the PWRGDx output pin will be high-impedance when the FB pin voltage is
higher than V
FBH
and will pull down to GND when the FB pin voltage is less than V
FBL
.
For the (2) options, the /PWRGDx output pin will be high-impedance when the FB pin voltage is
lower than V
FBL
and will pull down to GND when the FB pin voltage is higher than V
FBH
.
Each PWRGD output pin is connected to an open-drain, N-channel transistor implemented with
high-voltage structures. These transistors are capable of operating with pull-up resistors to supply
voltages as high as 100V.
To use this signal as a logic control in low-voltage DC/DC conversion applications, an external
pull-up resistor between this pin and the logic supply voltage is recommended, unless an internal
pull-up impedance is provided by the DC/DC module or other device (load).
5
PWRGD2
(MIC2586-1)
(MIC2586R-1)
Active-HIGH
/PWRGD2
(MIC2586-2)
(MIC2586R-2)
Active-LOW
Power-is-Good 2 (PWRGD2 or /PWRGD2), Open-Drain Output: For the (1) option, this output
signal is asserted when the following is true: PWRGD1 = Asserted AND the PWRGD1-to-
PWRGD2 delay (t
PG(1-2)
) has elapsed, where t
PG(1-2)
is the time delay programmed by the
capacitor (C
PG
) connected to the PGTIMER pin. Once PWRGD1 is asserted, an internal current
source (I
CPG
) begins to charge C
PG
. When the voltage on C
PG
crosses the V
PG2
threshold
(typically, 0.625V), PWRGD2 is asserted. The same description above applies to the (2) option.
For further information, refer to the PWRGD1 and PGTIMER pin descriptions.
To use this signal as a logic control in low-voltage DC/DC conversion applications, an external
pull-up resistor between this pin and the logic supply voltage is recommended, unless internal
pull-up impedance is provided by the DC/DC module or other device (load).
7
PGTIMER
Power-is-Good Delay Timer: A capacitor (C
PG
) connected from this pin to GND sets a delay from
PWRGD1 to PWRGD2 (t
PG(1-2)
) and from PWRGD1 to PWRGD3 (t
PG(1-3)
). An internal current
source (I
CPG
) is used to charge C
PG
only after PWRGD1 has been asserted. The same description
applies to the active-LOW (2) output signals.
9
PWRGD3
(MIC2586-1)
(MIC2586R-1)
Active-HIGH
/PWRGD3
(MIC2586-2)
(MIC2586R-2)
Active-LOW
Power-is-Good Output 3 (PWRGD3 or /PWRGD3), Open-Drain Output: For the (1) option, this
output signal is asserted when the following is true: PWRGD1 = Asserted AND the PWRGD1-to-
PWRGD3 delay (t
PG(1-3)
) has elapsed, where t
PG(1-3)
is the time delay programmed by the
capacitor (C
PG
) connected to the PGTIMER pin. Once PWRGD1 is asserted, an internal current
source (I
CPG
) begins to charge C
PG
. When the voltage on C
PG
crosses the V
PG3
threshold
(typically, 1.25V), PWRGD3 is asserted. The same description above applies to the (2) option.
For further information, refer to the PWRGD1 and PGTIMER pin descriptions.
To use this signal as a logic control in low-voltage DC/DC conversion applications, an external
pull-up resistor between this pin and the logic supply voltage is recommended, unless internal
pull-up impedance is provided by the DC/DC module or other device (load).
10
TIMER
Current-Limit Response Timer: A capacitor connected from this pin to GND provides overcurrent
filtering to prevent nuisance tripping of the circuit breaker by setting the time (t
FLT
) for which the
controller is allowed to remain in current limit. Once the MIC2586 circuit breaker trips, the output
latches off. Under normal (steady-state) operation, the TIMER pin is held to GND by an internal
3.5礎 current source (I
TIMERDN
). When the voltage across the external sense resistor exceeds the
V
TRIP
threshold, an internal 65礎 current source (I
TIMERUP
) is activated to charge the capacitor
connected to the TIMER pin. When the TIMER pin voltage reaches the V
TIMERH
threshold, the
circuit breaker is tripped pulling the GATE pin low, the I
TIMERUP
current source is disabled, and the
TIMER pin capacitor is discharged by the I
TIMERDN
current source. When the voltage at the TIMER
pin is less than 0.5V, the MIC2586 can be restarted by toggling the ON pin LOW then HIGH.
For the MIC2586R, the capacitor connected to the TIMER pin sets the period of auto-retry where
the duty cycle is fixed at a nominal 5%.
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