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參數(shù)資料
| 型號(hào)： | MIC2310-2ZTS TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 5/34頁 |
| 文件大小： | 473K |
| 描述： | IC HOT SWAP CTLR 2CHAN 24TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | 通用 |
| 內(nèi)部開關(guān)： | 無 |
| 電流限制： | 可調(diào) |
| 電源電壓： | 10.8 V ~ 13.2 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
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Micrel, Inc.
MIC2310
July 2008
5
M9999-070108-A
Pin Description (continued)
Pin Number
Pin Name
Pin Function
11
CSLEW
Inrush Current Slew Rate Control Input. To adjust the inrush load current profile
(controlled dI
DRAIN
/dt), connect a capacitor from this pin to VCC. To adjust the
MOSFET GATE voltage profile (controlled dV
GATE
/dt), leave this pin OPEN
(floating) and connect a capacitor from GATE to AGND. For additional
information on the operation of this function, please refer to the Functional
Description section.
12
AGND
Analog Ground. Connect this pin to the system analog ground plane.
13
HW_FLT
External MOSFET Hardware Fault Digital Output. This output is an open-drain,
active-HIGH signal that should be connected to a +3.3V logic supply by a 10k&
resistor. This digital output is active after the internal POR timer has terminated
and becomes asserted (HIGH) due to a fault under the following conditions: a) a
shorted DG MOSFET with ENABLE = LOW; b) a shorted DS MOSFET with
ENABLE = LOW; c) a shorted R
SENSE
; d) a shorted DS MOSFET after steady-
state operation with ENABLE = HIGH-to-LOW; or e) a shorted DG or DS while
EN = HIGH and DISCH = HIGH; or f) a shorted C
PRIMARY
to AGND. The
HW_FLT output is latched and is reset when VCC is brought low such that
V
REG
< V
VREG(UVLO)
.
14
PWRGD
/PWRGD
Power Good Digital Output. This output is an open-drain, active-HIGH (PWRGD)
or active-LOW (/PWRGD) signal that should be connected to a +3.3-V logic
supply by a 10k& resistor. This digital output is active after the internal POR
timer has terminated and becomes asserted when the voltage between the
LOADSENSE and the GNDSENSE pins is higher than the controllers V
PGH
threshold voltage. It is de-asserted when the voltage between the LOADSENSE
and the GNDSENSE pins is less than the controllers V
PGL
threshold voltage.
15
I_FLT
/I_FLT
Load Current Fault Digital Output. This output is an open-drain, active-HIGH
(I_FLT) or active-LOW (/I_FLT) signal that should be connected to a +3.3V logic
supply by a 10k& resistor. This digital output is active after the internal POR
timer has terminated and becomes asserted whenever the primary or secondary
overcurrent detection circuits cause the internal circuit breaker to latch OFF. The
digital output remains asserted unless the ENABLE input is toggled HIGH-to-
LOW-to-HIGH as defined by t
ENLPW
or the V
CC
supply voltage is turned OFF then
ON or if the auto-retry mode is enabled.
16
DISCH
Discharge External Transistor Drive Output. When ENABLE = LOW or after a
fault condition (either an overcurrent fault or hardware fault such as a shorted
MOSFET) that causes either the primary and secondary overcurrent detectors to
trip the internal circuit breaker, the DISCH circuit is activated to provide gate
drive to optional, external transistors (and SCR, for very fast load discharge).
These transistors serve as auxiliary gate pull-down or load voltage pull-down
switches. A load voltage pull-down is illustrated in the Typical Application circuit.
17
GNDSENSE
18
LOADSENSE
These input pins (when used together) sense the load voltage and provide
feedback to the controllers adaptive VA limit and Power-Good circuits. The
voltage across these two pins also sets the controllers Power-Is-Good status
output as defined by the specified V
PGH
or the V
PGL
threshold voltages. Internal
circuit monitors are included if either or both LOADSENSE and GNDSENSE
connections are severed or not connected to the load.
19
SOURCE
External Power MOSFET Source Pin Monitor. To protect external circuits
downstream of the controller, internal monitor circuits are included to sense a
shorted drain-source condition of the external power MOSFETs.
20
CPGND
Internal charge pump power ground. Connect this pin directly to the systems
analog ground plane.
21
GATE
External N-channel MOSFET GATE Drive Output. The GATE output signal uses
an internal charge pump to charge the gate of an external N-channel MOSFET
pass transistor.
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