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參數(shù)資料
| 型號： | MIC2086-MBQS TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 15/29頁 |
| 文件大小： | 1008K |
| 描述： | IC CTRLR HOW SWAP SGL 20-QSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | 通用型 Infiniband? |
| 內(nèi)部開關(guān)： | 無 |
| 電源電壓： | 2.3 V ~ 16.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-QSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | MIC2086-MBQSTR MIC2086-MBQSTR-ND |
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Micrel, Inc.
MIC2085/2086
May 2006
15
M9999-050406
(408) 955-1690
ms
V
2.73
2200礔
6A
/dt
d
Rate,
Slew
Voltage
Output
VOUT
=
=
and the resulting t
OCSLOW
needed to achieve a 12V
output is approximately 4.5ms. (See Power-On Reset,
Start-Up, and Overcurrent Timer Delays section to
calculate t
OCSLOW
.)
GATE Capacitance Dominated Start-Up
In this case, the value of the load capacitance relative to
the GATE capacitance is small enough such that the
load current during start-up never exceeds the current
limit threshold as determined by Equation 3. The
minimum value of C
GATE
that will ensure that the current
limit is never exceeded is given by the equation below:
LOAD
LIM
GATE
GATE
C
I
I
(min)
C
?/DIV>
=
(5)
where C
GATE
is the summation of the MOSFET input
capacitance (C
ISS
) and the value of the external
capacitor connected to the GATE pin of the MOSFET.
Once CGATE is determined, use the following equation
to determine the output slew rate for gate capacitance
dominated start-up.
(
)
GATE
GATE
OUT
C
I
output
/dt
dV
=
(6)
Table 1 depicts the output slew rate for various values of
C
GATE
.
I
GATE
= 15礎(chǔ)
CGATE
dVOUT/dt
0.001礔
15V/ms
0.01礔
1.5V/ms
0.1礔
0.150V/ms
1礔
0.015 礔/ms
Table 1. Output Slew Rate Selection for GATE
Capacitance Dominated Start-Up
Current Limiting and Dual-Level Circuit Breaker
Many applications will require that the inrush and steady
state supply current be limited at a specific value in order
to protect critical components within the system.
Connecting a sense resistor between the VCC and
SENSE pins sets the nominal current limit value of the
MIC2085/86 and the current limit is calculated using
Equation 2. However, the MIC2085/86 exhibits foldback
current limit response. The foldback feature allows the
nominal current limit threshold to vary from 24mVup to
48mV as the FB pin voltage increases or decreases.
When FB is at 0V, the current limit threshold is 24mV
and for FB e 0.6V, the current limit threshold is the
nominal 48mV.(See Figure 4 for Foldback Current Limit
Response characteristic).The MIC2085/86 also features
a dual-level circuit breaker triggered via 48mV and 95mV
current limit thresholds sensed across the VCC and
SENSE pins. The first level of the circuit breaker
functions as follows. Once the voltage sensed across
these two pins exceeds 48mV, the overcurrent timer, its
duration set by capacitor CFILTER, starts to ramp the
voltage at CFILTER using a 2礎(chǔ) constant current
source. If the voltage at CFILTER reaches the
overcurrent timer threshold (VTH) of 1.24V, then
CFILTER immediately returns to ground as the circuit
breaker trips and the GATE output is immediately shut
down. For the second level, if the voltage sensed across
VCC and SENSE exceeds 95mV at any time, the circuit
breaker trips and the GATE shuts down immediately,
bypassing the overcurrent timer period. To disable
current limit and circuit breaker operation, tie the SENSE
and VCC pins together and the CFILTER pin to ground.
Output Undervoltage Detection
The MIC2085/86 employ output undervoltage detection
by monitoring the output voltage through a resistive
divider connected at the FB pin. During turn on, while the
voltage at the FB pin is below the threshold (V
FB
), the
/POR pin is asserted low. Once the FB pin voltage
crosses V
FB
, a 2礎(chǔ) current source charges capacitor
C
POR
. Once the CPOR pin voltage reaches 1.24V, the
time period t
POR
elapses as the CPOR pin is pulled to
ground and the /POR pin goes HIGH. If the voltage at
FB drops below V
FB
for more than 10祍, the/POR pin
resets for at least one timing cycle defined by t
POR
(see
Applications Information for an example).
Input Overvoltage Protection
The MIC2085/86 monitors and detects overvoltage
conditions in the event of excessive supply transients at
the input. Whenever the overvoltage threshold (V
OV
) is
exceeded at the OV pin, the GATE is pulled low and the
output is shut off. The GATE will begin ramping one
POR timing cycle after the OV pin voltage drops below
its threshold. An external CRWBR circuit, as shown in
the typical application diagram, provides a time period
that an overvoltage condition must exceed in order to trip
the circuit breaker. When the OV pin exceeds the
overvoltage threshold (V
OV
), the CRWBR timer begins
charging the CRWBR capacitor initially with a 45礎(chǔ)
current source.Once the voltage at CRWBR exceeds its
threshold (V
CR
) of 0.47V, the CRWBR current
immediately increases to 1.5mA and the circuit breaker
is tripped, necessitating a device reset by toggling the
ON pin LOW to HIGH.
Power-On Reset, Start-Up, and Overcurrent
TimerDelays
The Power-On Reset delay, t
POR
, is the time period for
the /POR pin to go HIGH once the voltage at the FB pin
exceeds the power-good threshold (V
TH
). A capacitor
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