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參數(shù)資料
| 型號(hào)： | MH64D72KLG-10 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| 中文描述： | 4831838208位（67108864 - Word的72位），雙數(shù)據(jù)速率同步DRAM模塊 |
| 文件頁數(shù)： | 37/38頁 |
| 文件大小： | 326K |
| 代理商： | MH64D72KLG-10 |
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MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH64D72KLG-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0389-1.1
20.Nov.2000
Preliminary Spec.
Some contents are subject to change without notice.
37
Serial Presence Detect Table II
31
Density of each bank on module
512MByte
80
36-61
Superset Information (may be used in future)
option
00
62
SPD Revision
63
Checksum for bytes 0-62
Check sum for -10
64-71
Manufactures Jedec ID code per JEP-108E
MITSUBISHI
1CFFFFFFFFFFFFFF
72
Manufacturing location
Manufacture location
XX
73-90
Manufactures Part Number
91-92
93-94
Revision Code
Manufacturing date
PCB revision
year/week code
rrrr
yyww
95-98
Assembly Serial Number
Reserved
serial number
ssssssss
99-127
128-255
Undefined
Undefined
00
00
32
Command and Address signal input setup time
33
Command and Address signal input hold time
34
Data signal input setup time
35
Data signal input hold time
0
00
Check sum for -75
MH64D72KLG-75
MH64D72KLG-10
4D4836344437324B4C472D37352020202020
4D4836344437324B4C472D31302020202020
-75
-10
-75
-10
-75
-10
-75
-10
0.9nS
1.2nS
0.9nS
1.2nS
0.5nS
0.6nS
0.5nS
0.6nS
Open for Customer Use
90
C0
90
C0
50
60
50
60
10
B6
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MH64D72KLG-75 | 4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64D72KLH-10 | 4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64D72KLH-75 | 4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64S64APFH-6 | 4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM |
| MH64S64APFH-6L | 4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MH64D72KLG-75 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64D72KLH-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64D72KLH-75 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64FAD | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator |
| MH64FAD-R | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator |
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