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參數(shù)資料
| 型號： | MH16D72AKLB-75 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | JT 41C 41#20 PIN GRND PLUG |
| 中文描述： | 1,207.959,552位（16,777,216 - Word的72位），雙數(shù)據(jù)速率同步DRAM模塊 |
| 文件頁數(shù)： | 35/39頁 |
| 文件大小： | 348K |
| 代理商： | MH16D72AKLB-75 |
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MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0397-1.1
24.Nov.2000
Preliminary Spec.
Some contents are subject to change without notice.
35
[Power DOWN]
The purpose of CLK suspend is power down. CKE is synchronous input except during the self-refresh
mode. A command at cycle is ignored. From CKE=H to normal function, DLL recovery time is NOT
required in the condition of the stable CLK operation during the power down mode.
/CLK
CLK
Power Down by CKE
Command
PRE
CKE
Command
ACT
CKE
Standby Power Down
Active Power Down
NOP
NOP
Command
DQS
DQ
DM
Write
READ
D0
D1
[DM CONTROL]
DM is defined as the data mask for writes. During writes,DM masks input data word by word. DM to
write mask latency is 0.
D3
D4
D5
D6
D7
masked by DM=H
Don't Care
Q2
Q3
Q4
Q5
/CLK
CLK
Q0
Q1
Q6
Valid
NOP
NOP
Valid
tXPNR/
tXPRD
DM Function(BL=8,CL=2(Discrete))
Module input and output timing.
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PDF描述 |
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