參數(shù)資料
型號(hào)： MG65P
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： 0.25レm Embedded DRAM/ Customer Structured Arrays
中文描述： 0.25レ米嵌入式DRAM /客戶結(jié)構(gòu)數(shù)組
文件頁(yè)數(shù)： 16/22頁(yè)
文件大?。?/td> 267K
代理商： MG65P
I
MG63P/64P/65P
I
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14
Oki Semiconductor
Automatic Test Pattern Generation
Oki’s 0.25μm ASIC technologies support ATPG using full scan-path design techniques, including the fol-
lowing:
Increases fault coverage
≥
95%
Uses Synopsys Test Compiler
Automatically inserts scan structures
Connects scan chains
Traces and reports scan chains
Checks for rule violations
Generates complete fault reports
Allows multiple scan chains
Supports vector compaction
ATPG methodology is described in detail in Oki’s
0.25μm Scan Path Application Note
.
Floorplanning Design Flow
Oki offers two floorplanning tools for high-density ASIC design: Cadence DP3, and Gambit GFP. The
two main purposes for Oki’s floorplanning tools are to:
Ensure conformance of critical circuit performance specifications
Shorten overall design TAT
In a traditional design approach with synthesis tools, timing violations after prelayout simulation are
fixed by manual editing of the netlist. This process is difficult and time consuming. Also, there is no
physical cluster information provided in the synthesis tool, and so it is difficult to synthesize logic using
predicted interconnection delay due to wire length. Synthesis tools may therefore create over-optimized
results.
To minimize these problems, Synopsys proposed a methodology called, “Links to Layout (LTL)”. Based
on this methodology, Oki developed an interface between Oki’s Floorplanner and the Synopsys environ-
ment, called Link Synopsys to Floorplanner (LSF). As not every Synopsys user has access to the Synopsys
Floorplan Management tool, Oki had developed the LSF system to support both users who can access
Synopsys Floorplan Management and users who do not have access to Synopsys Floorplan Manage-
ment.
Scan Data In
Scan Select
D
C
SD
SS
Q
QN
D
C
SD
SS
A
B
Combinational Logic
FD1AS
FD1AS
Scan Data Out
Q
QN
Figure 14. Full Scan Path Configuration
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