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參數(shù)資料
| 型號： | MG64P |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 0.25レm Embedded DRAM/ Customer Structured Arrays |
| 中文描述： | 0.25レ米嵌入式DRAM /客戶結構數(shù)組 |
| 文件頁數(shù)： | 15/22頁 |
| 文件大小： | 267K |
| 代理商： | MG64P |
–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
I
MG63P/64P/65P
I
13
Oki Semiconductor
Design Process
The following figure illustrates the overall IC design process, also indicating the three main interface
points between external design houses and Oki ASIC Application Engineering.
Floorplanning
Scan Insertion (Optional)
CDC
[1]
Test Vectors
VHDL/HDL Description
Test Vector Conversion
(Oki TPL
)
Netlist Conversion
(EDIF 200)
TDC
[3]
Pre-Layout Simulation
(Cadence Verilog)
Layout
Automatic Test
Pattern Generation
(Synopsys Test Compiler)
Verification
(Cadence DRACULA)
Post-Layout Simulation
(Cadence Verilog)
Manufacturing
Prototype
Test Program
Conversion
Level 1
[5]
Level 2
Level 2.5
[5]
Level 3
[5]
CAE Front-End
Oki Interface
[1] Oki’s Circuit Data Check program (CDC) verifies logic design rules
[2] Oki’s Link to Synthesis Floorplanning toolset (LSF) transfers post-floorplanning timing for resynthesis
[3] Oki’s Test Data Check program (TDC) verifies test vector rules
[4] Oki’s Test Pattern Language (TPL)
[5] Alternate Customer-Oki design interfaces available in addition to standard level 2
[6] Standard design process includes fault simulation
Gate-Level Simulation
Floorplanning
LSF
[2]
Synthesis
Fault Simulation
[6]
Figure 13. Oki’s Design Process
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