參數(shù)資料
型號(hào): MFR4310E1MAE40
廠商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 微控制器/微處理器
英文描述: 2 CHANNEL(S), 10M bps, SERIAL COMM CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, 0.50 PITCH, LEAD FREE, MS-026BCD, LQFP-64
文件頁(yè)數(shù): 218/268頁(yè)
文件大?。?/td> 1718K
代理商: MFR4310E1MAE40
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Device Overview
MFR4310 Reference Manual, Rev. 1
Freescale Semiconductor
53
Figure 2-9 shows how to connect the CC to an HCS12 MCU with EBI paged mode support.
Figure 2-10 shows how to connect he CC to an HCS12 MCU with EBI unpaged mode support.
The HCS12 interface supports the paged and the unpaged modes of the HCS12 External Bus
Interface connected to it.
The HCS12 interface is implemented as an synchronous HCS12 External Bus slave module, thus
enabling the fast data exchange between them.
The HCS12 interface decodes the addresses of read/write transactions to its internal registers, and
generates its internal chip select signal, CS, using the address/data lines PA[0:7], PB[0:7],
ACS[0:2], and XADDR[14:19]:
— The address and data lines PA[0:7], PB[0:7] are multiplexed. They are denoted ADR[0:15]
when referring to the address, and DATA[0:15] when referring to the data. The FlexRay CC is
selected only when the address ADR[13:15] matches ACS[0:2] (ADR13 matches ACS0,
ADR12 matches ACS1, etc.) and the address XADDR[14:19] matches 0.
The HCS12 interface accepts only aligned 16-bit read and 8-bit or 16-bit write transactions. The
HCS12 interface does not support 8-bit read accesses.
— The internal chip select, CS, the low byte strobe, LSTRB, the least significant bit of the address,
ADR0, and the read/write select, RW_CC#, are used to determine the type of access, as shown
RW_CC# indicates the direction of data transfer for a transaction.
INT_CC# is an interrupt line that can be used for requesting, by means of the internal interrupt
controller, a service routine from the HCS12 device.
Table 2-10. HCS12 Access Types
CS
RW_CC#
LSTRB
ADR0
Type of Access
0
X
No access
1
0
16-bit write to word address1
1 Write data from PA to even byte address and from PB to odd byte address.
1
0
1
8-bit write to an odd address2
2 Write data from PB.
1
0
1
0
8-bit write to an even address2
10
11
Not supported
1
0
16-bit read from an even address3
3 Read data from even byte address at PA and from odd byte address at PB.
11
01
Not supported
11
10
Not supported
11
Not supported
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