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參數(shù)資料
| 型號： | MESC-PM1 |
| 廠商： | Lineage Power |
| 英文描述： | Enhanced Services Controller， Performance Monitor - 127 Connections(可執(zhí)行檢測127個(gè)連接的增強(qiáng)型服務(wù)控制器) |
| 中文描述： | 增強(qiáng)服務(wù)控制器，性能監(jiān)視器- 127連接（可執(zhí)行檢測127個(gè)連接的增強(qiáng)型服務(wù)控制器） |
| 文件頁數(shù)： | 1/15頁 |
| 文件大?。?/td> | 503K |
| 代理商： | MESC-PM1 |
Features
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Adjunct device to the Lucent ATM Port Controller (APC version 3) in ORCA 3T FPGA
PM function carried out at the PM Sink only (destination of Forward PM cells)
Extends the functionnality already available within the APC
Directly connected to the Transmit ESI Interface of a single APC
Maintain a different set of per VC statistics for up to 127 connections simultaneously
Ingress Received Cell Blocks (for convenience called - Stat 0)
Ingress Received CLP0+1 User Information Cells in a Block (for convenience called - Stat 1)
Ingress Severely Errored Cell Blocks (Bellcore GR1248 PM - Stat A)
Ingress CLP0+1 Errored Cells (Bellcore GR1248 PM - Stat B)
Ingress Lost CLP0+1 User Information Cells (Bellcore GR1248 PM - Stat C)
Ingress Misinserted CLP0+1 User Information Cells (Bellcore GR1248 PM - Stat E)
Ingress Total Transmitted CLP0+1 User Information Cells (Bellcore GR1248 PM - Stat F)
Handle four Block size type per channel : 128, 256, 512 and 1024 cells
Handle independant threshold for Lost, Misinserted and Errored statistics
Simple CPU interface with Ready signal
Available in VHDL source code format for ease of customization
Can be customised by Logic Design Solutions
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General Description
The MESC_PM1 function, implemented on a ORCA FPGA, is to extend the functionnality already available within the
APC.
L.D.S. can integrate your decoding logic in the FPGA in addition to any other predesigned functions.
Design Package
Device Family
PFUs
I/O
ORCA 3T80-7-S208
411 – 85% used
*
64
**
Bitstream + Data Sheet
VHDL Source code
1
Package file options
2
VHDL Test Bench
for behavioural and gate level simulation.
Data Sheet
Design Document
:
features, architecture, interfaces and operation.
User’s guide :
Simulation, Synthesis and Place and Route procedures.
Constraint Files :
.prf file
VHDL synthesis Leonardo Spectrum from Exemplar.
VHDL ModelSim simulation tool from ModelTech.
ORCA Foundry from Lucent Technologies.
Support provided by Logic Design Solutions 90 days e-mail and telephone support
from Logic Design Solutions included in the Macro price. Support does not cover
user Macro modifications. Maintenance Contracts available.
* Synthesis option dependant (area/speed)
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Assuming all Macro signals are routed off chip.
Design Tool Used
Support
Data Sheet
Apr. 2000 – Ver. 3
MESC-PM1
Enhanced Services Controller
MACRO
Performance Monitor - 127 Connections
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MESC-PM2 | Enhanced Services Controller， Performance Monitor - 32 Connections(可執(zhí)行檢測32個(gè)連接的增強(qiáng)型服務(wù)控制器) |
| MESC-PM3 | Enhanced Services Controller， Performance Monitor -127 Connections(可執(zhí)行檢測127個(gè)連接的增強(qiáng)型服務(wù)控制器) |
| MESC-PM4 | Enhanced Services Controller， Performance Monitor - 32 Connections(可執(zhí)行檢測32個(gè)連接的增強(qiáng)型服務(wù)控制器) |
| MESC-ST1 | Enhanced Services Controller，Statistics Monitor - 65535 Connections(可統(tǒng)計(jì)檢測65535個(gè)連接的增強(qiáng)型服務(wù)控制器) |
| MF1010S-1 | FOR AMPS MOBILE TELEPHONE, Tx |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MESP211D | 制造商:B&B Electronics Manufacturing Company 功能描述:MODBUS ETH 1PORT SERIAL SERVER |
| MESP211T | 制造商:B&B Electronics Manufacturing Company 功能描述:MODBUS ETH 1PORT SERIAL SERVER |
| MESR321 | 制造商:B&B Electronics Manufacturing Company 功能描述:MODBUS ESS ISO RJ45 232/422/485 |
| MESR321-ML | 制造商:B&B Electronics Manufacturing Company 功能描述:MODBUS ISO ESS RJ45 MM LC |
| MESR321-SL | 制造商:B&B Electronics Manufacturing Company 功能描述:MODBUS ISO ESS 1 RJ45 SM LC |
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