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參數(shù)資料
| 型號： | MESC-ST1 |
| 廠商： | Lineage Power |
| 英文描述： | Enhanced Services Controller，Statistics Monitor - 65535 Connections(可統(tǒng)計檢測65535個連接的增強型服務(wù)控制器) |
| 中文描述： | 增強服務(wù)控制器，統(tǒng)計監(jiān)測- 65535連接（可統(tǒng)計檢測65535個連接的增強型服務(wù)控制器） |
| 文件頁數(shù)： | 1/31頁 |
| 文件大?。?/td> | 182K |
| 代理商： | MESC-ST1 |
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Features
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Adjunct device to the Lucent ATM Port Controller (APC version 3) in ORCA 3T FPGA
Extends the statistics available to the microprocessor
Directly connected to the Transmit ESI Interface of a single APC
Maintain a different set of per Connection Statistics for up to 65535 connections simultaneously
Ingress Received Cells CLP
P
(
C
ell
L
oss
P
riority) (for convenience called – e_stat_0)
Egress Transmitted Cells CLP
P
(for convenience called - e_stat_1)
Minimum and Maximum Period CLP
P
Ingress Sustained Cell Rate CLP
P
(for convenience called - e_stat_2)
Ingress Sustained Cell Rate Violation Count CLP
P
Ingress Maximum Burst Size CLP
P
Maintain a different set of per Connection Discard Thresholds Statistics for up to 65535 connections simultaneously
Ingress Cells Discarded due to Buffer management CLP
P
(for convenience called - e_stat_3)
Ingress Cells Discarded due to Policing CLP
P
(for convenience called - e_stat_4)
Ingress Frames Discarded due to Buffer management CLP
P
(for convenience called - e_stat_5)
Ingress Frames Discarded due to Policing CLP
P
(for convenience called - e_stat_6)
Egress Cells Discarded due to Buffer management CLP
P
(for convenience called - e_stat_8)
Egress Frames Discarded due to Buffer management CLP
P
(for convenience called - e_stat_9)
Maintain a different set of per PHY Port Statistics for up to 32 ports simultaneously
Ingress Received Cells (for convenience called – phy_stat_0)
Egress Transmitted Cells (for convenience called - phy_stat_1)
Simple multiplexed address/data CPU interface with Ready signal
Available in VHDL source code format for ease of customization
Can be customised by Logic Design Solutions
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Design Package
Device Family
PFUs
I/O
ORCA 3T125-7-BGA352
82% used
*
133
(169) **
Bitstream + Data Sheet
VHDL Source code
1
Package file options
2
VHDL Test Bench
for behavioural and gate level simulation.
Data Sheet
User’s guide :
Simulation, Synthesis and Place and Route procedures.
Constraint Files :
.prf file
VHDL synthesis Leonardo Spectrum from Exemplar.
VHDL ModelSim simulation tool from ModelTech.
ORCA Foundry from Lucent Technologies.
Support provided by Logic Design Solutions 90 days e-mail and telephone support
from Logic Design Solutions included in the Macro price. Support does not cover user
Macro modifications. Maintenance Contracts available.
* Synthesis option dependant (area/speed)
**
Assuming all Macro signals are routed off chip. (169 I/Os, when incuding probe pins).
Design Tool Used
Support
Data Sheet
August. 2000 – Ver. 9
MESC-ST1
Enhanced Services Controller
MACRO
Statistics Monitor - 65535 Connections
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相關(guān)代理商/技術(shù)參數(shù) |
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| MESP211D | 制造商:B&B Electronics Manufacturing Company 功能描述:MODBUS ETH 1PORT SERIAL SERVER |
| MESP211T | 制造商:B&B Electronics Manufacturing Company 功能描述:MODBUS ETH 1PORT SERIAL SERVER |
| MESR321 | 制造商:B&B Electronics Manufacturing Company 功能描述:MODBUS ESS ISO RJ45 232/422/485 |
| MESR321-ML | 制造商:B&B Electronics Manufacturing Company 功能描述:MODBUS ISO ESS RJ45 MM LC |
| MESR321-SL | 制造商:B&B Electronics Manufacturing Company 功能描述:MODBUS ISO ESS 1 RJ45 SM LC |
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