參數(shù)資料
型號: MDS212
廠商: Zarlink Semiconductor Inc.
英文描述: 12-Port 10/100Mbps Ethernet Switch
中文描述: 12端口10/100Mbps以太網(wǎng)交換機
文件頁數(shù): 93/111頁
文件大小: 1609K
代理商: MDS212
MDS212
Data Sheet
93
Zarlink Semiconductor Inc.
Bit[15:11]
Bit[11]
Bit[12]
Bit[13]
Bit[14]
Bit[15]
Bit [30:16]
Bit [31]
Table bit map
MCID
VMAP
BMCT
FCB
QCNT
Reserve
C_RDY
Bit maps of five tables.
MCID=1 Use MC ID l Table
VMAP=1 Use VLAN port mapping Table (VMAP)
BMCT=1 Use Buffer Manager Control Table (BM control)
FCB=1 Use FCB Table
QCNT=1 Use Transmission Queue control Table (QM control)
Command Ready
0=Not Ready
1=Ready
18.2.11.9 CPUIRDAT - CPU Internal RAM Data Register
The 3 data registers are used when CPU reads or writes the content of the specified entry table.
CPUIRDAT0
CPU Internal RAM Data register for Data[31:0]
Address:
h588
CPUIRDAT1
CPU Internal RAM Data register for Data[63:32]
Address:
h58C
CPUIRDAT2
CPU Internal RAM Data register for Data[95:64]
Address:
h590
Access:
Non-Zero-Wait-State,
Direct Access,
Write/Read
The content is dependent on the type of table, as described below:
Type = MC ID (6bits)
Bit [5:0]
MCID
multicast ID FIFO data output
(Note that up to 16 for this version.)
Bit [31:6]
Reserved
Type = VMAP Table (27 bits)
Bit [11:0]
VLAN Port Enable [12:0]one bit for each Ethernet MAC Port
Identify the ports associated with each VLAN
0 = disable
Reserved
VLAN Tag Enable [12:0]one bit for each Ethernet MAC Port
0 = disable
1 = enable
Bit [12]
Bit [24:13]
1 = enable
31
0
CPIRDAT0
Data[31:0]
CPIRDAT1
Data[63:32]
CPIRDAT2
Data[95:64]
31
13 12
6
5
0
CPIRDAT0
MCID[5:0]
31
27
26
25
24
13
12
11
0
CPIRDAT0
RE
VLAN Tag Enable [12:0]
VLAN Port Enable [12:0]
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參數(shù)描述
MDS212CG 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:12-Port 10/100Mbps Ethernet Switch
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