參數(shù)資料
型號: MDS212
廠商: Zarlink Semiconductor Inc.
英文描述: 12-Port 10/100Mbps Ethernet Switch
中文描述: 12端口10/100Mbps以太網交換機
文件頁數(shù): 11/111頁
文件大小: 1609K
代理商: MDS212
MDS212
Data Sheet
11
Zarlink Semiconductor Inc.
1.0 Ball-signal Description and Assignments
VCC
AGND
= 3.3VDC for I/O 16 (balls)
= Isolated Analog Ground for AVDD (1 ball)
1
2
3
4
5
6
7
8
9
10
X_D
O16
X_D
O18
X_D
O19
X_D
O23
11
X_D
O13
X_D
O14
X_D
O15
X_D
O17
VCC X_D
12
X_D
O8
X_D
O10
X_D
O12
X_D
O11
13
X_D
O5
X_D
O4
X_D
O6
X_D
O7
GND X_D
14
X_D
O2
X_D
O3
X_D
O1
X_DE
NO
15
16
17
X_DI
25
X_DI
23
X_DI
22
X_DI
19
18
19
X_DI
17
X_DI
16
X_DI
14
X_DI
9
20
21
X_DI
8
X_DI
7
X_DI
6
X_DI
1
22
23
X_DI
2
X_DC
LKI
Rese
rved
P_IN
T
24
25
26
A AGND L_A2
0
L_A1
9
L_A1
8
Rese
rved
L_A1
1
L_A1
4
L_A1
7
NC L_A1
L_A8 L_A4 X_D
O29
X_D
O25
X_D
O26
X_D
O28
X_D
O20
X_D
O21
X_D
O24
X_DC
LKO
X_FC
O
X_DI
31
X_DI
30
X_DI
26
X_DI
29
X_DI
28
X_DI
27
X_DI
24
VCC X_DI
X_DI
21
X_DI
20
X_DI
18
X_DI
15
VDD X_DI
X_DI
12
X_DI
11
X_DI
10
X_DI
5
VCC P_G
X_DI
4
X_DI
3
X_DN
I
X_FC
I
GND P_AD
P_CS
I#
Rese
rved
P_RE
QC
P_RD
Y#
P_A1
0
P_RE
Q1
NC
P_GN
TC
NC
B
Reser
ved
Rese
rved
L_A1
0
L_A1
3
L_A5 X_D
O30
C AVDD Rese
rved
L_A6 X_D
O31
L_A7 L_A3 X_D
P_BR
DY#
P_RS
T#
P_CL
K
P_BL
AST
P_A8
D
L_D4 L_D1 L_CL
K
6
L_A1
2
O27
E
L_D6 L_D5 L_D2 L_D0 GND L_A1
5
VCC L_A9 VDD X_D
O22
O9
O0
13
0
NT1
S#
P_A7
F L_D11L_D1
0
L_D8 L_D3 T_M
ODE
#
P_R
WC#
P_A9 P_A4 P_A3 P_A2
G
L_D1
5
L_D2
0
L_D2
4
L_D2
9
L_WE
O#
L_D1
4
L_D1
8
L_D2
3
L_D2
7
L_D3
1
L_OE
0#
L_AD
S#
L_B
W4
L_D3
4
L_D3
8
L_D4
2
L_D4
5
L_D5
0
L_D5
4
L_D1
3
L_D1
6
L_D2
1
L_D2
6
L_D3
0
L_W
E1#
L_B
W2#
L_B
W7
L_D3
6
L_D3
9
L_D4
3
L_D4
8
L_D5
2
L_D5
5
L_D7 VCC
VCC P_A6 P_D3
1
P_D3
0
P_D2
6
P_D2
1
P_D1
8
P_D1
3
P_D9P_D8
P_D2
9
P_D2
4
P_D2
0
P_D1
6
P_D1
2
H
L_D1
2
L_D1
7
L_D2
2
L_D2
8
L_OE
1#
L_B
W1#
L_B
W6
L_D3
5
L_D4
1
L_D4
6
L_D5
1
L_D5
6
L_D6
1
L_D9
P_A5 P_A1 P_D2
8
J
VDD
VDD P_D2
7
P_D2
3
P_D1
9
P_D1
4
P_D1
1
K
L_D1
9
VCC
P_D2
5
VCC P_D1
P_D2
2
L
GND GND GND GND GND GND
7
M L_BW
0#
L_D2
5
S_CL
K
VDD
GND GND GND GND GND GND
P_D1
5
VDD P_D7P_D6P_D4P_D5
P_D1
0
N L_BW
3#
GND GND GND GND GND GND
P L_BW
5
GND GND GND GND GND GND
P_D0 T_D0 P_D1P_D3P_D2
R
L_D3
3
L_D3
7
L_D4
0
L_D4
4
L_D3
2
VCC
GND GND GND GND GND GND
T_D1
0
VCC T_D9 T_D7 T_D6 T_D5
T_D4 T_D3 T_D2 T_D1
T
GND GND GND GND GND GND
U
L_D4
7
VDD
T_D2
0
VDD T_D1
T_D1
5
T_D1
2
T_D1
6
T_D2
1
T_D2
4
T_D1
1
T_D1
4
T_D1
8
T_D2
3
T_D8
V
9
T_D1
3
T_D1
7
T_D2
2
W L_D4
9
L_D5
7
PM_
DO[1]
VCC PM_
T_D2
5
Y
L_D5
3
VCC
DEN
O
LE_#
SYN
CI
M_M
DC
AA L_D5
8
L_D5
9
L_D6
0
M_CL
KI
M0_T
XD0
NC
PM_
DI[1]
PM_
DI[0]
PM_
DENI
AB L_D6
2
L_D6
3
M0_T
XEN
M0_C
RS_D
V
M1_T
XEN
GND
M2_L
NK
VCC
M3_
CRS
_DV
M4_L
NK
VDD
M5_L
NK
VCC
M6_T
XD1
M8_T
XD0 GND
M9_T
XD1 VCC
M10_
RXD1VDD
M11_
TXD0VCC
NC
GND
LE_#
CLK
O
M_M
DIO
LE_S
YNC
O
LE_D
I
PM_
DO[0]
AC M0_L
NK
M0_T
XD1
M0_R
XD1
M2_T
XD1
M2_
RXD
1
M3_T
XD0
M3_T
XD1
M4_
RXD
1
M5_T
XD1
M5_T
XD0
M6_T
XEN
M7_L
NK
M7_C
RS_D
V
M7_R
XD1
M8_R
XD1
M9_T
XEN
M10_
TXEN
M10_
RXD0
M11_
RXD1 NC
NC
NC
NC
NC
LE_D
O
AD NC M0_R
XD0
M1_T
XD1
M2_T
XEN
M2_C
RS_D
V
M3_L
NK
M4_T
XEN
M4_
CRS
_DV
M4_
RXD
0
M5_T
XEN
M5_
RXD
0
M6_L
NK
M6_C
RS_D
V
M6_R
XD1
M7_T
XEN
M8_C
RS_D
V
M8_T
XEN
M9_T
XD0
M9_R
XD0
M10_
TXD0
M11-
TXEN
M11_
RXD0 NC
NC
NC
NC
NC
NC
NC
AE NC M1_L
NK
M1_R
XD0
M2_T
XD0
M3_
RXD
1
M3_
RXD
0
M4_T
XD1
M5_
CRS
_DV
M5_
RXD
1
M7_T
XD1
M8_L
NK
M9_L
NK
M9_R
XD1
M10_
TXD1
M11_
LNK
M11_
CRS_
DV
M11_
TXD1 NC
NC
NC
NC
NC
NC
NC
NC
AF M1_T
XD0
M1_C
RS_
DV
2
M1_R
XD1
M2_R
XD0
M3_T
XEN
M4_T
XD0
M6_T
XD0
M6_R
XD0
M7_T
XD0
M7_R
XD0
M8_T
XD1
M8_R
XD0
M9_C
RS_
DV
16
M10_
LNK
M10_
CRS_
DV
NC
NC
NC
NC
NC
NC
1
3
4
5
6
7
8
9
10
11
12
13
14
15
17
18
19
20
21
22
23
24
25
26
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