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參數(shù)資料
| 型號： | MD82C55A-5/B |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 24 I/O, PIA-GENERAL PURPOSE, CDIP40 |
| 封裝： | FRIT SEALED, CERDIP-40 |
| 文件頁數(shù)： | 22/26頁 |
| 文件大?。?/td> | 581K |
| 代理商： | MD82C55A-5/B |
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5
The modes for Port A and Port B can be separately defined,
while Port C is divided into two portions as required by the
Port A and Port B definitions. All of the output registers,
including the status flip-flops, will be reset whenever the
mode is changed. Modes may be combined so that their
functional definition can be “tailored” to almost any I/O
structure. For instance: Group B can be programmed in
Mode 0 to monitor simple switch closings or display compu-
tational results, Group A could be programmed in Mode 1 to
monitor a keyboard or tape reader on an interrupt-driven
basis.
The mode definitions and possible mode combinations may
seem confusing at first, but after a cursory review of the
complete device operation a simple, logical I/O approach will
surface. The design of the 82C55A has taken into account
things such as efficient PC board layout, control signal defi-
nition vs. PC layout and complete functional flexibility to sup-
port almost any peripheral device with no external logic.
Such design represents the maximum use of the available
pins.
Single Bit Set/Reset Feature (Figure 5)
Any of the eight bits of Port C can be Set or Reset using a
single Output instruction. This feature reduces software
requirements in control-based applications.
When Port C is being used as status/control for Port A or B,
these bits can be set or reset by using the Bit Set/Reset
operation just as if they were output ports.
Interrupt Control Functions
When the 82C55A is programmed to operate in mode 1 or
mode 2, control signals are provided that can be used as
interrupt request inputs to the CPU. The interrupt request
signals, generated from port C, can be inhibited or enabled
by setting or resetting the associated INTE flip-flop, using the
bit set/reset function of port C.
This function allows the programmer to enable or disable a
CPU interrupt by a specific I/O device without affecting any
other device in the interrupt structure.
INTE Flip-Flop Definition
(BIT-SET)-INTE is SET - Interrupt Enable
(BIT-RESET)-INTE is Reset - Interrupt Disable
NOTE:
All Mask flip-flops are automatically reset during mode se-
lection and device Reset.
Operating Modes
Mode 0 (Basic Input/Output). This functional configuration
provides simple input and output operations for each of the
three ports. No handshaking is required, data is simply writ-
ten to or read from a specific port.
Mode 0 Basic Functional Definitions:
Two 8-bit ports and two 4-bit ports
Any Port can be input or output
Outputs are latched
Input are not latched
16 different Input/Output configurations possible
FIGURE 5. BIT SET/RESET FORMAT
D7 D6 D5
D4 D3 D2
D1 D0
BIT SET/RESET
1 = SET
0 = RESET
BIT SELECT
0
BIT SET/RESET FLAG
CONTROL WORD
DON’T
CARE
X
0 = ACTIVE
1234 567
01010 101
00110 011
00001 111
B0
B1
B2
MODE 0 PORT DEFINITION
AB
GROUP A
#
GROUP B
D4
D3
D1
D0
PORT A
PORTC
(Upper)
PORT B
PORTC
(Lower)
0
Output
0
Output
0
1
Output
1
Output
Input
0
1
0
Output
2
Input
Output
0
1
Output
3
Input
0
1
0
Output
Input
4
Output
0
1
0
1
Output
Input
5
Output
Input
0
1
0
Output
Input
6
Input
Output
0
1
Output
Input
7
Input
1
0
Input
Output
8
Output
1
0
1
Input
Output
9
Output
Input
1
0
1
0
Input
Output
10
Input
Output
1
0
1
Input
Output
11
Input
1
0
Input
12
Output
1
0
1
Input
13
Output
Input
1
0
Input
14
Input
Output
1
Input
15
Input
82C55A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MR82C55A-5/B | 24 I/O, PIA-GENERAL PURPOSE, CQCC44 |
| MR82C55A/B | 24 I/O, PIA-GENERAL PURPOSE, CQCC44 |
| MD82C59A-5/B | 80C86; 80C88; 80C286; 8080; 8085; 8086; 8088; 80286; NSC800 COMPATIBLE, INTERRUPT CONTROLLER, CDIP28 |
| MR82C59A/B | 80C86; 80C88; 80C286; 8080; 8085; 8086; 8088; 80286; NSC800 COMPATIBLE, INTERRUPT CONTROLLER, CQCC28 |
| MD82C59A-12/B | 80C86; 80C88; 80C286; 8080; 8085; 8086; 8088; 80286; NSC800 COMPATIBLE, INTERRUPT CONTROLLER, CDIP28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MD82C55AB | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Programmable Peripheral Interface |
| MD82C55B | 制造商:HARRIS 制造商全稱:HARRIS 功能描述:CMOS Programmable Peripheral Interface |
| MD82C59A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Priority Interrupt Controller |
| MD82C59A WAF | 制造商:Harris Corporation 功能描述: |
| MD82C59A/7 | 制造商:Intersil Corporation 功能描述:PRIORITY INTERRUPT CONTROLLER, THIN EPI - Rail/Tube |
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