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參數(shù)資料
| 型號(hào)： | MD80C52XXX-12MQ |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | CERAMIC, DIP-40 |
| 文件頁(yè)數(shù)： | 257/313頁(yè) |
| 文件大?。?/td> | 4988K |
| 代理商： | MD80C52XXX-12MQ |
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48
32000D–04/2011
AVR32
5.3.3
MMU exception handling
This chapter describes the software actions that must be performed for MMU-related excep-
tions. The hardware actions performed by the exceptions are described in detail in Section 8.3.1
5.3.3.1
ITLB / DTLB Multiple Hit
If multiple matching entries are found when searching the ITLB or DTLB, this exception is
issued. This situation is a critical error, since memory consistency can no longer be guaranteed.
The exception hardware therefore jumps to the reset vector, where software should execute the
required reset code. This exception is a sign of erroneous code and is not normally generated.
The software handler should perform a normal system restart. However, debugging code may
be inserted in the handler.
5.3.3.2
ITLB / DTLB Miss
This exception is issued if no matching entries are found in the TLBs, or when a matching entry
is found with the Valid bit cleared. The same actions must be performed for both exceptions, but
DTLB entries contains more control bits than the ITLB entries.
1.
Examine the TLBEAR and TLBEHI registers in order to identify the page that caused
the fault. Use this to index the page table pointed to by PTBR and fetch the desired
page table entry.
2.
Use the fetched page table entry to update the necessary bits in PTEHI and PTELO.
The following bits must be updated, not all bits apply to ITLB entries: V, PFN, C, G, B,
AP[2:0], SZ[1:0], W, D.
3.
The TLBEHI[I] register is updated by hardware to indicate if it was a ITLB or a DTLB
miss. The MMUCR[IRP] and MMUCR[DRP] pointers may be updated in an IMPLE-
MENTATION DEFINED way in order to select which TLB entry to replace. The software
may override this value by writing a value directly to MMUCR[IRP] or MMUCR[DRP],
depending on which TLB to update.
4.
Execute the tlbw instruction in order to update the TLB entry.
5.
Finish the exception handling and return to the application by executing the rete
instruction.
5.3.3.3
ITLB / DTLB Protection Violation
This exception is issued if the access permision bits in the matching TLB entry does not match
the privilege level the CPU is currently executing in. The exception is also issued if the MMU is
disabled or absent and non-translated areas are accessed with illegal access rights. The same
actions must be performed for both exceptions, but DTLB entries contains more control bits than
the ITLB entries.
Software must examine the TLBEAR and TLBEHI registers in order to identify the instruction
and process that caused the error. Corrective measures like terminating the process must then
be performed before returning to normal execution with rete.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MR80C52TXXX-16P883R | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44 |
| MQ80C52CXXX-16/883D | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44 |
| MQ80C32-30/883D | 8-BIT, 30 MHz, MICROCONTROLLER, CQFP44 |
| MR80C32E-12SC | 8-BIT, 12 MHz, MICROCONTROLLER, CQCC44 |
| MD80C32-36SCD | 8-BIT, 36 MHz, MICROCONTROLLER, CDIP40 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MD80C86 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MD80C862 | 制造商:Intel 功能描述:PROCESSOR:MICRO-PROCESSOR |
| MD80C86-2 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MD80C86-2/883 | 制造商:Intersil Corporation 功能描述:MPU 16BIT CMOS 8MHZ 40CDIP - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:CPU 16BILT 5V CMOS 8MHZ 40CDIP - Bulk |
| MD80C86-2/B | 制造商:Intersil Corporation 功能描述:MPU 16BIT CMOS 8MHZ 40CDIP - Rail/Tube |
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