
315
ATmega64A [DATASHEET]
8160D–AVR–02/2013
Notes:
1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.
2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.
6t
AVWL
Address Valid to WR Low
235
1.0t
CLCL-15
ns
7tLLWL
ALE Low to WR Low
115
130
0.5tCLCL+5
ns
8t
LLRL
ALE Low to RD Low
115
130
0.5t
0.5t
CLCL+5
ns
9tDVRH
Data Setup to RD High
45
ns
10
tRLDV
Read Low to Data Valid
190
1.0tCLCL-60
ns
11
t
RHDX
Data Hold After RD High
0
ns
12
tRLRH
RD Pulse Width
235
1.0tCLCL-15
ns
13
tDVWL
Data Setup to WR Low
105
ns
14
t
WHDX
Data Hold After WR High
235
1.0t
CLCL-15
ns
15
tDVWH
Data Valid to WR High
250
1.0tCLCL
ns
16
tWLWH
WR Pulse Width
235
1.0tCLCL-15
ns
Table 29-12. External Data Memory Characteristics, 2.7 - 5.5 volts, No Wait-state (Continued)
Symbol
Parameter
4 MHz Oscillator
Variable Oscillator
Unit
Min
Max
Min
Max
Table 29-13. External Data Memory Characteristics, 2.7 - 5.5 volts, SRWn1 = 0, SRWn0 = 1
Symbol
Parameter
4 MHz Oscillator
Variable Oscillator
Unit
Min
Max
Min
Max
01/tCLCL
Oscillator Frequency
0.0
8
MHz
10
t
RLDV
Read Low to Data Valid
440
2.0t
CLCL-60
ns
12
tRLRH
RD Pulse Width
485
2.0tCLCL-15
ns
15
t
DVWH
Data Valid to WR High
500
2.0t
CLCL
ns
16
t
WLWH
WR Pulse Width
485
2.0t
CLCL-15
ns
Table 29-14. External Data Memory Characteristics, 2.7 - 5.5 volts, SRWn1 = 1, SRWn0 = 0
Symbol
Parameter
4 MHz Oscillator
Variable Oscillator
Unit
Min
Max
Min
Max
01/t
CLCL
Oscillator Frequency
0.0
8
MHz
10
tRLDV
Read Low to Data Valid
690
3.0tCLCL-60
ns
12
t
RLRH
RD Pulse Width
735
3.0t
CLCL-15
ns
15
t
DVWH
Data Valid to WR High
750
3.0t
CLCL
ns
16
tWLWH
WR Pulse Width
735
3.0tCLCL-15
ns
Table 29-15. External Data Memory Characteristics, 2.7 - 5.5 volts, SRWn1 = 1, SRWn0 = 1
Symbol
Parameter
4 MHz Oscillator
Variable Oscillator
Unit
Min
Max
Min
Max
01/tCLCL
Oscillator Frequency
0.0
8
MHz
10
t
RLDV
Read Low to Data Valid
690
3.0t
CLCL-60
ns
12
tRLRH
RD Pulse Width
735
3.0tCLCL-15
ns