
27
ATmega64A [DATASHEET]
8160D–AVR–02/2013
8.6
Register Description
8.6.1
MCUCR – MCU Control Register
Bit 7 – SRE: External SRAM/XMEM Enable
Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8, ALE, WR, and RD are
activated as the alternate pin functions. The SRE bit overrides any pin direction settings in the respective data
direction registers. Writing SRE to zero, disables the External Memory Interface and the normal pin and data direc-
tion settings are used.
Bit 6 – SRW10: Wait State Select Bit
For a detailed description in non ATmega103 compatibility mode, see common description for the SRWn bits
below (XMRA description). In ATmega103 compatibility mode, writing SRW10 to one enables the wait state and
one extra cycle is added during read/write strobe as shown in
Figure 8-7.
8.6.2
XMCRA – External Memory Control Register A
Bit 7 – Res: Reserved Bit
This is a reserved bit and will always read as zero. When writing to this address location, write this bit to zero for
compatibility with future devices.
Bit 6:4 – SRL2, SRL1, SRL0: Wait State Sector Limit
It is possible to configure different wait states for different external memory addresses. The external memory
address space can be divided in two sectors that have separate wait-state bits. The SRL2, SRL1, and SRL0 bits
select the split of the sectors, see
Table 8-2 and
Figure 8-4. By default, the SRL2, SRL1, and SRL0 bits are set to
zero and the entire external memory address space is treated as one sector. When the entire SRAM address
space is configured as one sector, the wait states are configured by the SRW11 and SRW10 bits.
Bit
765
43210
SRE
SRW10
SE
SM1
SM0
SM2
IVSEL
IVCE
MCUCR
Read/Write
R/W
Initial Value
000
00000
Bit
765
43210
–
SRL2
SRL1
SRL0
SRW01
SRW00
SRW11
–
XMCRA
Read/Write
R
R/W
R
Initial Value
000
00000