參數(shù)資料
型號: MCZ34653EFR2
廠商: Freescale Semiconductor
文件頁數(shù): 16/24頁
文件大?。?/td> 1649K
描述: IC HOTSWAP CTRLR 1A NEG 8-SOIC
標(biāo)準(zhǔn)包裝: 2,500
類型: 熱交換開關(guān)
應(yīng)用: 通用
內(nèi)部開關(guān):
電流限制: 1A
電源電壓: 36 V ~ 80 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOICN
包裝: 帶卷 (TR)
Analog Integrated Circuit Device Data
16
Freescale Semiconductor
34653
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSIS FEATURES
rchived by Freescale Semiconductor, Inc., 2008
Table 5. Thermal Resistance Data
Type
Condition
Symbol Value  Unit
Junction to Ambient
Single-layer board (1s), per JEDEC jesd51-2 with board (JESD51-3) horizontal
R
?/DIV>
JA
167
癈/W
Junction to Ambient
Four-layer board (2s2p), per JEDEC JESD51-2 with board (JESD51-3) horizontal
R
?/DIV>
JMA
115
癈/W
Junction to Ambient
Single-layer board with a 300 mm
2
 radiator pad on its top surface, not standard JEDEC
    145
癈/W
Junction to Ambient
Single-layer board with a 600 mm
2
 radiator pad on its top surface, not standard JEDEC
    143
癈/W
Junction to Ambient
Four-layer board with a via for each thermal lead, not standard JEDEC
    111   ?/SPAN>C/W
Junction to Ambient
Four-layer board with a 300 mm
2
 radiator pad on its top surface and a full array of vias
between radiator pad and top surface, not standard JEDEC
    107   ?/SPAN>C/W
Junction to Ambient
Four-layer board with a 600 mm
2
 radiator pad on its top surface and a full array of vias
between radiator pad and top surface, not standard JEDEC
    107   ?/SPAN>C/W
Junction to Board
Thermal resistance between die and board per JEDEC JESD51-8
R
窲B
62   ?/SPAN>C/W
Junction to Case
Thermal resistance between die and case top
R
窲C
57   ?/SPAN>C/W
Junction to Package
Top
Temperature difference between package top and junction per JEDEC JESD51-2
?/DIV>
JT
18   ?/SPAN>C/W
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