
Analog Integrated Circuit Device Data
Freescale Semiconductor
28
33977
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
SO COMMUNICATION
When the CS pin is pulled low, the internal status register,
as configured with the PECCR command bits PE11:PE8, is
loaded into the output register and the data is clocked out
MSB (OD15) first. Following a CS
transition 0 to 1, the device
determines if the shifted-in message was of a valid length (a
valid message length is one that is greater than 0 bits and a
multiple of 16 bits) and, if so, latches the incoming data into
the appropriate registers. At this time, the SO pin is tri-stated
and the status register is now able to accept new status
information. Fault status information will be latched and held
until the Device Status Output register is selected and it is
clocked out via the SO. If the message length was
determined to be invalid, the fault information will not be
cleared and will be transmitted again during the next valid SPI
message. Pointer status information bits (e.g., pointer
position, velocity, and commanded position status) will
always reflect the real time state of the pointer. Any bits
clocked out of the SO pin after the first 16 are representative
of the initial message bits clocked into the SI pin since the
CS
pin first transitioned to a Logic [0]. This feature is useful for
daisy-chaining devices as well as message verification. As
described above, the last valid write to bits PE11:PE8 of the
PECCR command determines the nature of the status data
that is clocked out of the SO pin. There are four different
types of status information available:
1. Device Status (
Table 16
)
2. RTZ Accumulator Status (
Table 17
)
3. Gauge Pointer Position Status (
Table 18
)
4. Gauge Pointer Velocity Status (
Table 19
)
Once a specific status type is selected, it will not change
until either the PECCR command bits PE11:PE8 (D11:D8)
are written to select another or the device is reset. Each of the
Status types and the PECCR bit necessary to select them ar
described in the following paragraphs.
DEVICE STATUS INFORMATION
Most recent valid PECCR command resulting in the Device
Status output:
The bits in
Table 16
are
read-only
bits.
(ST15) Bit OD15
This bit has no meaning.
(DIR) Bit OD14
This bit indicates the direction that the Gauge is moving.
0 = Toward position 0
1 = Away from position 0
(ST13) Bit OD13
This bit has no meaning.
(0POS) Bit OD12
This bit indicates the configured Position 0 for the Gauge.
0 = Farthest CCW
1 = Farthest CW
(ST11) Bit OD11
This bit has no meaning.
(CMD) Bit OD10
This bit indicates if the Gauge is at the most recently
commanded position.
0 = At commanded position
1 = Not at commanded position
Overvoltage Indication (OV) Bit OD9
A Logic [1] on this bit indicates V
PWR
voltage exceeded the
upper limit of V
PWROV
since the last SPI communication.
Refer to the Static Electrical Characteristics
Table 3
under
POWER INPUT.
An overvoltage event will automatically disable the driver
outputs. Because the pointer may not be in the expected
position, the master may want to re-calibrate the pointer
position with an RTZ command after the voltage returns to a
normal level. For an overvoltage event, both gauges must be
re-enabled as quickly as this flag returns to Logic [0]. The
state machine will continue to operate properly as long as
V
DD
is within the normal range.
0 = Normal range
1 = Battery voltage exceeded V
PWROV
Undervoltage Indication (UV) Bit OD8
A Logic [1] on this bit indicates the V
PWR
voltage fell below
V
PWRUV
since the last SPI communication. Refer to the
Static
Electrical Characteristics
Table 3
under the heading of
POWER INPUT. An undervoltage event is just flagged;
however, at some voltage level below 4.0 V, the outputs turn
OFF and the state machine resets. Because the pointer may
D11
D10
D9
D8
0
x
x
x
x = Don’t Care
Table 16. Device Status Output Register
Bits
OD15
OD14
OD13
OD12
OD11
OD10
OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
Read
ST15
DIR
ST13
0POS
ST11
CMD
OV
UV
CAL
OVUV
ST5
MOV
ST3
RTZ
ST1
OT
Write
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–