參數(shù)資料
型號(hào): MCZ33800EK
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: Engine Control Integrated Circuit
中文描述: 發(fā)動(dòng)機(jī)控制集成電路
文件頁(yè)數(shù): 20/39頁(yè)
文件大?。?/td> 461K
代理商: MCZ33800EK
Analog Integrated Circuit Device Data
Freescale Semiconductor
20
33800
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
SPI AND MCU INTERFACE DESCRIPTION
The 33800 device directly interfaces to a 3.3 or 5.0V
microcontroller unit (MCU) using 16 bit Serial Peripheral
Interface (SPI) protocol. SPI serial clock frequencies up to
4.0MHz may be used when programming and reading output
status information (production tested at 1MHz).
Figure 6
illustrates the serial peripheral interface (SPI) configuration
between an MCU and one 33800.
Command data is sent to the 33800 device through the SI
input pin. As data is being clocked into the SI pin, status
information is being clocked out of the device by the SO
output pin. The response data received by the MCU during
SPI communication depends on the previous SPI message
sent to the device. The next SO response data is listed at the
bottom of each command table
( Table 7, on page 22, Table
12, on page 25, Table 22, on page 30 Table 23, on page 31
,
Table 26, on page 34
.
SPI Integrity Check
Checking the integrity of the SPI communication with the
initial power-up of the VDD and EN pins is recommended.
After initial system start-up or reset, the MCU will write one
32-bit pattern to the 33800. The first 16-bits read by the MCU
will be the fault status (SO message 1) of the outputs. The
second 16-bits will be the same bit pattern sent by the MCU.
By the MCU receiving the same bit pattern it sent, bus
integrity is confirmed. The second 16-bit pattern the MCU
sends to the device is the a command word and will be
operated on by the device accordingly on rising edge of
CS
.
Important
A SCLK pulse count strategy has been
implemented to ensure integrity of SPI communications. SPI
messages consisting of 16 SCLK pulses and multiples of 8
clock pulses thereafter will be acknowledged. SPI messages
consisting of other than 16 + multiples of 8 SCLK pulses will
be ignored by the device.
Figure 6. SPI Interface with Microprocessor
Two or more 33800 devices may be used in a module
system. Multiple ICs may be SPI-configured in parallel or
serial.
Figures 7
and
8
show the configurations. When using
the serial configuration, 32-clock cycles are required to
transfer data in / out of the ICs.
Figure 7. SPI Parallel Interface with Microprocessor
Figure 8. SPI Serial Interface with Microprocessor
PROGRAMMABLE PWM GATE DRIVER OUTPUTS
The 33800 device is designed with six flexible PWM gate
driver outputs. Each driver may be controlled directly from the
MCU or may be programmed through the SPI for a specific
frequency and duty cycle.
The pre-drivers are designed with four diagnostic features:
33800
Microcontroller
Receive
Buffer
Parallel
Ports
To Logic
16-Bit Shift Register
Shift Register
MOSI
SI
MISO
SO
SCLK
CS
Parallel
Ports
Microcontroller
33800
33800
SI
SCLK
CS
SI
SO
SCLK
CS
SCLK
MISO
MOSI
Shift Register
SO
Parallel
Ports
Microcontroller
33800
33800
SI
SCLK
CS
SI
SO
SCLK
CS
SO
SCLK
MISO
MOSI
Shift Register
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