參數(shù)資料
型號(hào): MCZ33800EK
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: Engine Control Integrated Circuit
中文描述: 發(fā)動(dòng)機(jī)控制集成電路
文件頁(yè)數(shù): 13/39頁(yè)
文件大小: 461K
代理商: MCZ33800EK
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
33800
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
OCTAL SERIAL DRIVERS (OUT1 - OUT8) (CONTINUED)
Output Off Open Circuit Fault Filter Timer
(11)
t
OC
400
500
650
μ
s
Output Slew Rate
R
LOAD
= 51
R
LOAD
= 51
t
SR(RISE)
t
SR(FALL)
1.0
1.0
5.0
5.0
10
10
V/
μ
s
P1 Input Propagation Delay
Input @ 50% V
DD
to Output voltage 10% of final value
Input @ 50% V
DD
to Output voltage 90% of initial value
t
(RISEDELAY)
t
(FALLDELAY)
6.0
6.0
μ
s
P3, P5, P7 Input Propagation Delay
Input @ 50% V
DD
to Output voltage 10% of final value
Input @ 50% V
DD
to Output voltage 90% of initial value
t
(RISEDELAY)
t
(FALLDELAY)
5.0
5.0
μ
s
OSCILLATOR AND TIMER ACCURACY
Calibrated Timer Accuracy
(11)
t
TIMER
±
10
%
Un-calibrated Timer Accuracy
t
TIMER
±
80
%
SPI DIGITAL INTERFACE TIMING (SO, SI, CS, SCLK)
(12)
Required Low State Duration on V
PWR
for Reset
(13)
V
PWR
0.2V
t
RESET
1.0
μ
s
Falling Edge of CS to Rising Edge of SCLK
Required Setup Time
t
LEAD
100
ns
Falling Edge of SCLK to Rising Edge of
CS
Required Setup Time
t
LAG
50
ns
SI to Rising Edge of SCLK
Required Setup Time
t
SI (SU)
16
ns
Rising Edge of SCLK to SI
Required Hold Time
t
SI (HOLD)
20
ns
SI,
CS
, SCLK Signal Rise Time
(14)
t
R (SI)
5.0
ns
SI,
CS
, SCLK Signal Fall Time
(14)
t
F (SI)
5.0
ns
Time from Falling Edge of
CS
to SO Low-impedance
(15)
t
SO (EN)
150
ns
Time from Rising Edge of
CS
to SO High-impedance
(16)
t
SO (DIS)
150
ns
Time from Falling Edge of SCLK to SO Data Valid
(17)
t
VALID
25
150
ns
Sequential Transfer Rate
Time required between data transfers
t
STR
1.0
μ
s
Notes
11.
12.
13.
14.
15.
16.
17.
Assumes oscillator has been calibrated using SPI Calibrate Command
These parameters are guaranteed by design. Production test equipment uses 1MHz, 5.0V SPI interface.
This parameter is guaranteed by design, however it is not production tested.
Rise and Fall time of incoming SI,
CS
, and SCLK signals for design consideration to prevent the occurrence of double pulsing.
Time required for valid output status data to be available on SO pin.
Time required for output states data to be terminated at SO pin.
Time required to obtain valid data out from SO following the fall of SCLK with 200pF load.
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 3.0V
V
DD
5.5V, 9.0V
V
PWR
18V, - 40
°
C
T
A
125
°
C, GND = 0V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at T
A
= 25°C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
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