參數(shù)資料
型號(hào)： MCZ33689DEW
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： System Basis Chip with LIN Transceiver
中文描述： 系統(tǒng)基礎(chǔ)芯片的LIN收發(fā)器
文件頁(yè)數(shù)： 25/31頁(yè)
文件大?。?/td> 309K
代理商： MCZ33689DEW
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
33689
FUNCTIONAL DESCRIPTION
FUNCTIONAL DEVICE OPERATION
LIN-PU — LIN Pullup Enable Bit
This bit controls the LIN pullup resistor during Sleep and
Stop modes in accordance with
Table 4
. Reset clears the
LIN-PU bit.
HS3: HS1 — High-Side H3 : HS1 Enable Bits
These bits enable the HS3 HS1 bits in accordance with
Table 5
. Reset clears the HSx bit.
Note
If no PWM on HS1 and HS2 is required, the IN pin
must be connected to the VDD pin.
MODE2 and MODE1 — Mode Section Bits
The MODE2 and MODE1 bits control the 33689 operating
modes in accordance with
Table 6
.
To safely enter Sleep or Stop mode and to ensure that
these modes are not affected by noise issue during SPI
transmission, the Sleep Stop commands require two SPI
transmissions.
Sleep Mode Sequence
The Sleep command, as shown in
Table 7
, must be sent twice.
Stop Mode Sequence
The Stop command, as shown in
Table 8
, must be sent twice.
Table 4. LIN Pullup Termination Control Bit (D5)
LIN-PU
Description
0
30 k
pullup connected in Sleep and Stop mode
1
30 k
pullup disconnected in Sleep and Stop mode
Table 5. High-Side Switches Control Bits (D4, D3, and D2)
HS3
Description
HS2
Description
HS1
Description
0
HS3 OFF
0
HS2 OFF
0
HS1 OFF
1
HS3 ON
1
HS2 ON (if IN = 1)
1
HS1 ON (if IN = 1)
Table 6. Mode Control Bits (D1 and D0)
MODE2
MODE1
Description
0
0
Sleep mode
(3)
0
1
Stop mode
1
0
Normal mode + Watchdog clear
(4)
1
1
Normal mode
Notes
3.
Special SPI command and sequence is implemented in
order to avoid going into Sleep or Stop mode with a single
8-bit SPI command. Refer to
Tables 7
and
8
.
When a logic [0] is written to MODE1 bit while MODE2 bit
is written as a logic [1]. After the SPI command is
completed, MODE1 bit is set to logic [1] and the 33689
stays in Normal mode. In order to set the 33689 in Sleep
mode, both MODE1 and MODE2 bits must be written in
the same 8-bit SPI command. The Watchdog clear on
Normal Request mode (150 ms) has no window.
4.
Table 7. Sleep Command Bits
LINSL2
LINSL1
LIN-PU
HS3
HS2
HS1
MODE2
MODE1
1
1
x
0
0
0
0
0
x = Don’t care.
Table 8. Stop Command Bits
LINSL2
LINSL1
LIN-PU
HS3
HS2
HS1
MODE2
MODE1
1
1
x
0
0
0
0
1
x = Don’t care.
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