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參數(shù)資料
| 型號： | MCZ33689DEW |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | System Basis Chip with LIN Transceiver |
| 中文描述： | 系統(tǒng)基礎(chǔ)芯片的LIN收發(fā)器 |
| 文件頁數(shù)： | 13/31頁 |
| 文件大?。?/td> | 309K |
| 代理商： | MCZ33689DEW |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
13
33689
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
CURRENT SENSE OPERATIONAL AMPLIFIER
Supply Voltage Rejection Ratio
(16)
SVR
60
—
—
dB
Common Mode Rejection Ratio
(16)
CMR
70
—
—
dB
Gain Bandwidth
(16)
GBP
1.0
—
—
MHz
Output Slew Rate
SR
0.5
—
—
V/
μ
s
Phase Margin
PHMO
40
—
—
deg.
Open Loop Gain
(16)
OLG
—
85
—
dB
L1 AND L2 INPUT PINS
Wake-Up Filter Time
(16)
t
WUF
8.0
20
38
μ
s
STATE MACHINE TIMING
Delay Between
CS
LOW-to-HIGH Transition (at End of SPI Stop Command)
and Stop Mode Activation
(16)
Minimum Watchdog Period
No Watchdog Selected
Maximum Watchdog Period
t
STOP
1.4
6.0
12
—
—
—
5.0
30
50
μ
s
Interrupt Low-Level Duration
t
INT
7.0
10
13
μ
s
Internal Oscillator Frequency Accuracy (All Modes, for Information Only)
f
OSC
- 35
—
35
%
Normal Request Mode Time-Out (Normal Request Mode)
t
NRTOUT
97
150
205
ms
Delay Between SPI Command and HS1 or HS2 Turn On
(17)
,
(18)
Normal Mode, V
SUP
> 9.0 V, V
HS
≥
0.2 V
VS2
t
SHSON
—
—
20
μ
s
Delay Between SPI Command and HS1 or HS2 Turn Off
(17)
,
(18)
Normal Mode, V
SUP
> 9.0 V, V
HS
≤
0.8 V
VS2
t
SHSOFF
—
—
20
μ
s
Delay Between SPI Command and HS3 Turn On
(17)
,
(19)
Normal Mode, V
SUP
> 9.0 V, V
HS
≥
0.2 V
VS2
t
SHSON
—
—
20
μ
s
Delay Between SPI Command and HS3 Turn Off
(17)
,
(19)
Normal Mode, V
SUP
> 9.0 V, V
HS
≤
0.8 V
VS2
t
SHSOFF
—
—
20
μ
s
Delay Between Normal Request and Normal Mode After a Watchdog Trigger
Command (Normal Request Mode)
(16)
t
SNR2N
7.0
15
30
μ
s
Delay Between
CS
Wake-Up (
CS
LOW to HIGH) in Stop Mode and:
Normal Request Mode, VDD ON and
RST
HIGH
First Accepted SPI Command
t
WUCS
t
WUSPI
t
S1STSPI
15
90
40
—
80
N/A
μ
s
Delay Between Interrupt Pulse in Stop Mode After Wake-Up and First
Accepted SPI Command
30
—
N/A
μ
s
Minimum Time Between Rising and Falling Edge on the
CS
t
2
CS
15
—
—
μ
s
Notes
16.
17.
Parameter guaranteed by design; however, it is not production tested.
When IN input is set to HIGH, delay starts at falling edge of clock cycle #8 of the SPI command and start of device activation/deactivation.
30 mA load on high-side switches. Excluding rise or fall time due to external load.
When IN is used to control the high-side switches, delays are measured between IN and HS1 or HS2 ON OFF. 30 mA load on high-side
switches, excluding rise or fall time due to external load.
Delay between turn on or turn off command and HS ON or HS OFF, excluding rise or fall time due to external load.
18.
19.
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V
≤
V
SUP
≤
18 V, - 40
°
C
≤
T
A
≤
125
°
C, GND = 0.0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at T
A
= 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
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| MCZ33730EKR2 | 功能描述:線性穩(wěn)壓器 - 標準 SW MODE P/S W/ MULT REG RoHS:否 制造商:STMicroelectronics 輸出類型: 極性: 輸出電壓:1.8 V 輸出電流:150 mA 負載調(diào)節(jié): 最大輸入電壓:5.5 V 線路調(diào)整率: 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:SOT-323-5L |
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