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| 型號： | MCP6444T-E/SL |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 6/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP QUAD 1.6V 9KHZ 14SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,600 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 4 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 0.003 V/µs |
| 增益帶寬積： | 9kHz |
| 電流 - 輸入偏壓： | 1pA |
| 電壓 - 輸入偏移： | 4500µV |
| 電流 - 電源： | 0.45µA |
| 電流 - 輸出 / 通道： | 22mA |
| 電壓 - 電源，單路/雙路(±)： | 1.4 V ~ 6 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SOICN |
| 包裝： | 帶卷 (TR) |
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MCP6441/2/4
DS22257C-page 14
2010-2012 Microchip Technology Inc.
4.1.4
NORMAL OPERATION
The input stage of the MCP6441/2/4 op amp uses two
differential input stages in parallel. One operates at a
low Common Mode input voltage (VCM), while the other
operates at a high VCM. With this topology, the device
operates with a VCM up to 300 mV above VDD and
300 mV below VSS. The input offset voltage is
measured at VCM =VSS – 0.3V and VDD + 0.3V, to
ensure proper operation.
The transition between the input stages occurs when
the best distortion performance and gain linearity, with
non-inverting gains, avoid this region of operation.
4.2
Rail-to-Rail Output
The output voltage range of the MCP6441/2/4 op amp
is VSS + 20 mV (minimum) and VDD – 20 mV (maxi-
mum) when RL =10kΩ is connected to VDD/2 and
information.
4.3
Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases, and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. While a unity-gain buffer (G = +1 V/V) is the
most sensitive to the capacitive loads, all gains show
the same general behavior.
When
driving
large
capacitive
loads
with
the
MCP6441/2/4
op
amp
(e.g.,
> 100 pF
when
G = +1 V/V), a small series resistor at the output (RISO
in Figure 4-4) improves the feedback loop’s phase mar-
gin (stability) by making the output load resistive at
higher frequencies. The bandwidth will be generally
lower than the bandwidth with no capacitance load.
FIGURE 4-4:
Output Resistor, RISO
Stabilizes Large Capacitive Loads.
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit's noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
FIGURE 4-5:
Recommended RISO Values
for Capacitive Loads.
After selecting RISO for your circuit, double-check the
resulting
frequency
response
peaking
and
step
response overshoot. Modify RISO’s value until the
response
is
reasonable.
Bench
evaluation
and
simulations with the MCP6441/2/4 SPICE macro
model are very helpful.
4.4
Supply Bypass
The MCP6441/2/4 op amp’s power supply pin (VDD for
single-supply) should have a local bypass capacitor
(i.e., 0.01 F to 0.1 F) within 2 mm for good high
frequency performance. It can use a bulk capacitor
(i.e., 1 F or larger) within 100 mm to provide large,
slow currents. This bulk capacitor can be shared with
other analog parts.
4.5
PCB Surface Leakage
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012
Ω. A 5V difference would
cause 5 pA of current to flow, which is greater than the
MCP6441/2/4 op amp’s bias current at +25°C (±1 pA,
typical).
VIN
RISO
VOUT
CL
–
+
MCP644X
1000
10000
100000
1000000
1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06
Normalized Load Capacitance; CL/GN (F)
Re
c
o
m
en
d
ed
R
IS
O
(
)
GN:
1 V/V
2 V/V
≥ 5 V/V
10p
100p
1n
10n
0.1
1
1k
10k
100k
1M
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