2009 Microchip Technology Inc.
DS11177F-page 11
MCP606/7/8/9
Note: Unless otherwise indicated, V
DD = +2.5V to +5.5V, VSS = GND, TA =+25°C, VCM =VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 60 pF, and CS is tied low.
FIGURE 2-25:
Large-signal, Non-inverting
Pulse Response.
FIGURE 2-26:
Small-signal, Non-inverting
Pulse Response.
FIGURE 2-27:
Chip Select (CS) Hysteresis
(MCP608 only).
FIGURE 2-28:
Large-signal, Inverting
Pulse Response.
FIGURE 2-29:
Small-signal, Inverting Pulse
Response.
FIGURE 2-30:
Amplifier Output Response
Times vs. Chip Select (CS) Pulse (MCP608
only).
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Time (50 s/div)
Output
V
o
ltge
(V
)
VDD = 5.0V
Time (50 s/div)
Output
Voltag
e(20
mV/div
)
VDD = 5.0V
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0 0.5 1.01.5 2.02.5 3.03.5 4.04.5 5.0
CS Input Voltage (V)
Inte
rnal
CS
Switch
Output
(V
)
Amplifier Output Active
Amplifier Output Hi-Z
VDD = 5.0V
Hysteresis
CS Input
High to Low
CS Input
Low to High
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Time (50 s/div)
Output
V
o
lta
g
e
(V
)
VDD = 5.0V
Time (50 s/div)
Outp
ut
V
o
lta
g
e
(20
mV/div
)
RL = 25 k
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Time (5 s/div)
Output
Volt
ag
e(
V
)
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
Chip
S
e
le
ct
Voltage
(V
)
CS
VOUT
Output
Hi-Z
Output
Hi-Z
Output Enabled
G = +1 V/V
RL = 1 k to VSS