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| 型號： | MCP6002-I/SN |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 6/42頁 |
| 文件大小： | 0K |
| 描述： | IC OPAMP 1.8V 1MHZ DUAL 8-SOIC |
| 標準包裝： | 100 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 2 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 0.6 V/µs |
| 增益帶寬積： | 1MHz |
| 電流 - 輸入偏壓： | 1pA |
| 電壓 - 輸入偏移： | 4500µV |
| 電流 - 電源： | 100µA |
| 電流 - 輸出 / 通道： | 23mA |
| 電壓 - 電源，單路/雙路(±)： | 1.8 V ~ 6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOICN |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 678 (CN2011-ZH PDF) |
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MCP6001/1R/1U/2/4
DS21733J-page 14
2009 Microchip Technology Inc.
4.3
Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. While a unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, all gains show the same
general behavior.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitance load.
FIGURE 4-3:
Output resistor, RISO
stabilizes large capacitive loads.
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit's noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
FIGURE 4-4:
Recommended RISO values
for Capacitive Loads.
After selecting RISO for your circuit, double-check the
resulting
frequency
response
peaking
and
step
response overshoot. Modify RISO’s value until the
response
is
reasonable.
Bench
evaluation
and
simulations with the MCP6001/1R/1U/2/4 SPICE
macro model are very helpful.
4.4
Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single-supply) should have a local
bypass capacitor (i.e., 0.01 F to 0.1 F) within 2 mm
for good high-frequency performance. It also needs a
bulk capacitor (i.e., 1 F or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with nearby analog parts.
4.5
Unused Op Amps
An unused op amp in a quad package (MCP6004)
should be configured as shown in Figure 4-5. These
circuits prevent the output from toggling and causing
crosstalk. Circuits A sets the op amp at its minimum
noise gain. The resistor divider produces any desired
reference voltage within the output voltage range of the
op amp; the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
current.
FIGURE 4-5:
Unused Op Amps.
4.6
PCB Surface Leakage
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012
Ω. A 5V difference would
cause 5 pA of current to flow; which is greater than the
MCP6001/1R/1U/2/4 family’s bias current at 25°C (typ-
ically 1 pA).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
VIN
RISO
VOUT
MCP600X
CL
–
+
10
100
1000
1.E-11
1.E-10
1.E-09
1.E-08
Normalized Load Capacitance; CL/GN (F)
R
eco
m
en
d
e
d
R
IS
O
(
)
G
N = 1
G
N ≥ 2
10p
10n
100p
V
DD = 5.0V
R
L = 100 k
1n
VDD
MCP6004 (A)
MCP6004 (B)
R1
R2
VDD
VREF
V
REF
V
DD
R
2
R
1
R
2
+
------------------
=
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