參數(shù)資料
型號： MCP4541T-103E/MS
廠商： Microchip Technology
文件頁數(shù)： 65/92頁
文件大小： 0K
描述： IC POT DGTL 10K SGL 8-MSOP
標準包裝： 2,500
接片： 129
電阻（歐姆）： 10k
電路數(shù)： 1
溫度系數(shù)： 標準值 150 ppm/°C
存儲器類型： 非易失
接口： I²C（設(shè)備位址）
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 帶卷 (TR)
MCP454X/456X/464X/466X
DS22107A-page 68
2008 Microchip Technology Inc.
8.2
Using Shutdown
Figure 8-3 shows a possible application circuit where
the independent terminals could be used. Disconnect-
ing the wiper allows the transistor input to be taken to
the Bias voltage level (disconnecting A and or B may
be desired to reduce system current). Disconnecting
Terminal A modifies the transistor input by the RBW
rheostat value to the Common B. Disconnecting
Terminal B modifies the transistor input by the RAW
rheostat value to the Common A. The Common A and
Common B connections could be connected to VDD
and VSS.
FIGURE 8-3:
Example Application Circuit
using Terminal Disconnects.
8.3
Software Reset Sequence
At times it may become necessary to perform a Soft-
ware Reset Sequence to ensure the MCP45XX/46XX
device is in a correct and known I2C Interface state.
This technique only resets the I2C state machine.
This is useful if the MCP45XX/46XX device powers up
in an incorrect state (due to excessive bus noise, ...), or
if the Master Device is reset during communication.
Figure 8-4 shows the communication sequence to soft-
ware reset the device.
FIGURE 8-4:
Software Reset Sequence
Format.
The 1st Start bit will cause the device to reset from a
state in which it is expecting to receive data from the
Master Device. In this mode, the device is monitoring
the data bus in Receive mode and can detect the Start
bit forces an internal Reset.
The nine bits of ‘1’ are used to force a Reset of those
devices that could not be reset by the previous Start bit.
This occurs only if the MCP45XX/46XX is driving an A
bit on the I2C bus, or is in output mode (from a Read
command) and is driving a data bit of ‘0’ onto the I2C
bus. In both of these cases, the previous Start bit could
not be generated due to the MCP45XX/46XX holding
the bus low. By sending out nine ‘1’ bits, it is ensured
that the device will see a A bit (the Master Device does
not drive the I2C bus low to acknowledge the data sent
by the MCP45XX/46XX), which also forces the
MCP45XX/46XX to reset.
The 2nd Start bit is sent to address the rare possibility
of an erroneous write. This could occur if the Master
Device was reset while sending a Write command to
the MCP45XX/46XX, AND then as the Master Device
returns to normal operation and issues a Start condition
while the MCP45XX/46XX is issuing an Acknowledge.
In this case, if the 2nd Start bit is not sent (and the Stop
bit was sent) the MCP45XX/46XX could initiate a write
cycle.
The Stop bit terminates the current I2C bus activity. The
MCP45XX/46XX wait to detect the next Start condition.
This sequence does not effect any other I2C devices
which may be on the bus, as they should disregard this
as an invalid command.
Note:
This technique is documented in AN1028.
Balance
Bias
W
B
Input
To base
of Transistor
(or Amplifier)
A
Common B
Common A
Note:
The potential for this erroneous write
ONLY occurs if the Master Device is reset
while sending a Write command to the
MCP45XX/46XX.
S
‘1’
S
P
Start
bit
Nine bits of ‘1’
Start bit
Stop bit
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