I2C Bus Data " />
參數(shù)資料
型號： MCP4441-503E/ST
廠商： Microchip Technology
文件頁數(shù)： 7/100頁
文件大小： 0K
描述： IC DGTL POT 129TAPS QUAD 20TSSOP
標(biāo)準(zhǔn)包裝： 74
接片： 129
電阻（歐姆）： 50k
電路數(shù)： 4
溫度系數(shù)： 標(biāo)準(zhǔn)值 150 ppm/°C
存儲器類型： 非易失
接口： I²C（設(shè)備位址）
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 管件
MCP444X/446X
DS22265A-page 14
2010 Microchip Technology Inc.
FIGURE 1-3:
I2C Bus Data Timing.
90
91
92
100
101
103
106
107
109
110
102
SCL
SDA
In
SDA
Out
TABLE 1-3:
I2C BUS DATA REQUIREMENTS (SLAVE MODE)
I2C AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40
°C ≤ TA ≤ +125°C (Extended)
Operating Voltage VDD range is described in AC/DC characteristics
Param.
No.
Sym
Characteristic
Min
Max
Units
Conditions
100
THIGH
Clock high time
100 kHz mode
4000
—
ns
1.8V-5.5V
400 kHz mode
600
—
ns
2.7V-5.5V
1.7 MHz mode
120
ns
4.5V-5.5V
3.4 MHz mode
60
—
ns
4.5V-5.5V
101
TLOW
Clock low time
100 kHz mode
4700
—
ns
1.8V-5.5V
400 kHz mode
1300
—
ns
2.7V-5.5V
1.7 MHz mode
320
ns
4.5V-5.5V
3.4 MHz mode
160
—
ns
4.5V-5.5V
Note 1:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2:
A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the
requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line
TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before
the SCL line is released.
3:
The MCP44X1/MCP44X2 device must provide a data hold time to bridge the undefined part between VIH
and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but
must be tested in order to ensure that the output data will meet the setup and hold specifications for the
receiving device.
4:
Use Cb in pF for the calculations.
5:
Not Tested.
6:
A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
7:
Ensured by the TAA 3.4 MHz specification test.
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