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| 型號： | MCP4261T-104E/SL |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 57/88頁 |
| 文件大小： | 0K |
| 描述： | IC DGTL POT 100K 2CH 14SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,600 |
| 系列： | WiperLock™ |
| 接片： | 257 |
| 電阻（歐姆）： | 100k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 150 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | 4 線 SPI（芯片選擇） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SOIC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | MCP4261T-104-E/SL MCP4261T-104-E/SLTR MCP4261T-104-E/SLTR-ND MCP4261T-104E/SLTR |
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MCP414X/416X/424X/426X
DS22059B-page 60
2008 Microchip Technology Inc.
8.2
Techniques to force the CS pin to
VIHH
The circuit in Figure 8-3 shows a method using the
TC1240A doubling charge pump. When the SHDN pin
is high, the TC1240A is off, and the level on the CS pin
is controlled by the PIC microcontrollers (MCUs) IO2
pin.
When the SHDN pin is low, the TC1240A is on and the
VOUT voltage is 2 * VDD. The resistor R1 allows the CS
pin to go higher than the voltage such that the PIC
MCU’s IO2 pin “clamps” at approximately VDD.
FIGURE 8-3:
Using the TC1240A to
generate the VIHH voltage.
The circuit in Figure 8-4 shows the method used on the
MCP402X Non-volatile Digital Potentiometer Evalua-
tion Board (Part Number: MCP402XEV). This method
requires that the system voltage be approximately 5V.
This ensures that when the PIC10F206 enters a
brown-out condition, there is an insufficient voltage
level on the CS pin to change the stored value of the
wiper. The MCP402X Non-volatile Digital Potentiome-
ter Evaluation Board User’s Guide (DS51546) contains
a complete schematic.
GP0 is a general purpose I/O pin, while GP2 can either
be a general purpose I/O pin or it can output the internal
clock.
For the serial commands, configure the GP2 pin as an
input (high impedance). The output state of the GP0 pin
will determine the voltage on the CS pin (VIL or VIH).
For high-voltage serial commands, force the GP0
output pin to output a high level (VOH) and configure the
GP2 pin to output the internal clock. This will form a
charge pump and increase the voltage on the CS pin
(when the system voltage is approximately 5V).
FIGURE 8-4:
MCP4XXX Non-volatile
Digital Potentiometer Evaluation Board
(MCP402XEV) implementation to generate the
VIHH voltage.
8.3
Using Shutdown Modes
Figure 8-5 shows a possible application circuit where
the
independent
terminals
could
be
used.
Disconnecting the wiper allows the transistor input to
be taken to the Bias voltage level (disconnecting A and
or B may be desired to reduce system current).
Disconnecting Terminal A modifies the transistor input
by the RBW rheostat value to the Common B.
Disconnecting Terminal B modifies the transistor input
by the RAW rheostat value to the Common A. The
Common A and Common B connections could be
connected to VDD and VSS.
FIGURE 8-5:
Example Application Circuit
using Terminal Disconnects.
CS
PIC MCU
MCP402X
R1
IO1
IO2
C2
TC1240A
VIN
SHDN
C+
C-
VOUT
C1
CS
PIC10F206
MCP4XXX
R1
GP0
GP2
C2
C1
Balance
Bias
W
B
Input
To base
of Transistor
(or Amplifier)
A
Common B
Common A
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