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| 型號： | MCP4162T-503E/MS |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 31/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DGTL SNGL 50K RHEO 8MSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | WiperLock™ |
| 接片： | 257 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 150 ppm/°C |
| 存儲(chǔ)器類型： | 易失 |
| 接口： | 4 線 SPI（芯片選擇） |
| 電源電壓： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 帶卷 (TR) |
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2008 Microchip Technology Inc.
DS22059B-page 37
MCP414X/416X/424X/426X
5.4
Shutdown
Shutdown is used to minimize the device’s current
consumption. The MCP4XXX has two methods to
achieve this. These are:
The Hardware Shutdown pin is backwards compatible
with the MCP42XXX devices.
5.4.1
HARDWARE SHUTDOWN PIN
(SHDN)
The SHDN pin is available on the dual potentiometer
devices. When the SHDN pin is forced active (VIL):
The P0A and P1A terminals are disconnected
The P0W and P1W terminals are simultaneously
connect to the P0B and P1B terminals,
respectively (see Figure 5-2)
The Serial Interface is NOT disabled, and all
Serial Interface activity is executed
Any EEPROM write cycles are completed
The Hardware Shutdown pin mode does NOT corrupt
the values in the Volatile Wiper Registers nor the
TCON register. When the Shutdown mode is exited
(SHDN pin is inactive (VIH)):
The device returns to the Wiper setting specified
by the Volatile Wiper value
The TCON register bits return to controlling the
terminal connection state
FIGURE 5-2:
Hardware Shutdown
Resistor Network Configuration.
5.4.2
TERMINAL CONTROL REGISTER
(TCON)
The Terminal Control (TCON) register is a volatile
register used to configure the connection of each
resistor network terminal pin (A, B, and W) to the
Resistor
Network.
This
register
is
shown
in
The RxHW bits forces the selected resistor network
into the same state as the SHDN pin. Alternate low
power configurations may be achieved with the RxA,
RxW, and RxB bits.
5.4.3
INTERACTION OF SHDN PIN AND
TCON REGISTER
Figure 5-3 shows how the SHDN pin signal and the
RxHW bit signal interact to control the hardware
shutdown of each resistor network (independently).
Using the TCON bits allows each resistor network (Pot
0 and Pot 1) to be individually “shutdown” while the
hardware pin forces both resistor networks to be
“shutdown” at the same time.
FIGURE 5-3:
RxHW bit and SHDN pin
Interaction.
A
B
W
Resistor
Network
Note:
When the RxHW bit forces the resistor
network into the hardware SHDN state,
the state of the TCON register RxA, RxW,
and RxB bits is overridden (ignored).
When the state of the RxHW bit no longer
forces the resistor network into the
hardware SHDN state, the TCON register
RxA, RxW, and RxB bits return to control-
ling the terminal connection state. In other
words, the RxHW bit does not corrupt the
state of the RxA, RxW, and RxB bits.
SHDN (from pin)
RxHW
(from TCON register)
To Pot x Hardware
Shutdown Control
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