V
參數(shù)資料
型號(hào): MCP3204T-BI/SL
廠商: Microchip Technology
文件頁(yè)數(shù): 23/40頁(yè)
文件大?。?/td> 0K
描述: IC ADC 12BIT 2.7V 4CH SPI 14SOIC
標(biāo)準(zhǔn)包裝: 2,600
位數(shù): 12
采樣率(每秒): 100k
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 14-SOIC
包裝: 帶卷 (TR)
輸入數(shù)目和類(lèi)型: 4 個(gè)單端,單極;2 個(gè)偽差分,單極
2008 Microchip Technology Inc.
DS21298E-page 3
MCP3204/3208
Input Voltage Range for IN- in
pseudo-differential Mode
VSS-100
VSS+100
mV
Leakage Current
0.001
±1
A
Switch Resistance
1000
Sample Capacitor
20
pF
Digital Input/Output
Data Coding Format
Straight Binary
High Level Input Voltage
VIH
0.7 VDD
——
V
Low Level Input Voltage
VIL
0.3 VDD
V
High Level Output Voltage
VOH
4.1
V
IOH = -1 mA, VDD = 4.5V
Low Level Output Voltage
VOL
——
0.4
V
IOL = 1 mA, VDD = 4.5V
Input Leakage Current
ILI
-10
10
A
VIN = VSS or VDD
Output Leakage Current
ILO
-10
10
A
VOUT = VSS or VDD
Pin Capacitance
(All Inputs/Outputs)
CIN,COUT
——
10
pF
VDD = 5.0V (Note 1)
TA = 25°C, f = 1 MHz
Timing Parameters
Clock Frequency
fCLK
2.0
1.0
MHz
VDD = 5V (Note 3)
VDD = 2.7V (Note 3)
Clock High Time
tHI
250
ns
Clock Low Time
tLO
250
ns
CS Fall To First Rising CLK
Edge
tSUCS
100
ns
Data Input Setup Time
tSU
50
ns
Data Input Hold Time
tHD
50
ns
CLK Fall To Output Data Valid
tDO
200
ns
See Figures 1-2 and 1-3
CLK Fall To Output Enable
tEN
200
ns
See Figures 1-2 and 1-3
CS Rise To Output Disable
tDIS
100
ns
See Figures 1-2 and 1-3
CS Disable Time
tCSH
500
ns
D
OUT Rise Time
tR
100
ns
See Figures 1-2 and 1-3 (Note 1)
D
OUT Fall Time
tF
100
ns
See Figures 1-2 and 1-3 (Note 1)
Power Requirements
Operating Voltage
VDD
2.7
5.5
V
Operating Current
IDD
320
225
400
A
VDD=VREF = 5V, DOUT unloaded
VDD=VREF = 2.7V, DOUT unloaded
Standby Current
IDDS
—0.5
2.0
A
CS = VDD = 5.0V
ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics:
Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, VREF = 5V,
TA = -40°C to +85°C,fSAMPLE = 100 ksps and fCLK = 20*fSAMPLE
Parameters
Sym
Min
Typ
Max
Units
Conditions
Note 1:
This parameter is established by characterization and not 100% tested.
2:
See graphs that relate linearity performance to VREF levels.
3:
Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity
performance, particularly at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock
Speed”
, “Maintaining Minimum Clock Speed”, for more information.
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