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| 鍨嬭櫉锛� | MCP3204-BI/P |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 23/40闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC ADC 12BIT 2.7V 4CH SPI 14-DIP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 30 |
| 浣嶆暩(sh霉)锛� | 12 |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 100k |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶锛孲PI? |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 1 |
| 闆诲闆绘簮锛� | 鍠浕婧� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 閫氬瓟 |
| 灏佽/澶栨锛� | 14-DIP锛�0.300"锛�7.62mm锛� |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 14-PDIP |
| 鍖呰锛� | 绠′欢 |
| 杓稿叆鏁�(sh霉)鐩拰椤炲瀷锛� | 4 鍊嬪柈绔�锛屽柈妤�锛�2 鍊嬪伣宸垎锛屽柈妤� |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 672 (CN2011-ZH PDF) |
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2008 Microchip Technology Inc.
DS21298E-page 3
MCP3204/3208
Input Voltage Range for IN- in
pseudo-differential Mode
VSS-100
鈥�
VSS+100
mV
Leakage Current
鈥�
0.001
卤1
A
Switch Resistance
鈥�
1000
鈥�
See Figure 4-1
Sample Capacitor
鈥�
20
鈥�
pF
See Figure 4-1
Digital Input/Output
Data Coding Format
Straight Binary
High Level Input Voltage
VIH
0.7 VDD
鈥斺€�
V
Low Level Input Voltage
VIL
鈥�
0.3 VDD
V
High Level Output Voltage
VOH
4.1
鈥�
V
IOH = -1 mA, VDD = 4.5V
Low Level Output Voltage
VOL
鈥斺€�
0.4
V
IOL = 1 mA, VDD = 4.5V
Input Leakage Current
ILI
-10
鈥�
10
A
VIN = VSS or VDD
Output Leakage Current
ILO
-10
鈥�
10
A
VOUT = VSS or VDD
Pin Capacitance
(All Inputs/Outputs)
CIN,COUT
鈥斺€�
10
pF
TA = 25掳C, f = 1 MHz
Timing Parameters
Clock Frequency
fCLK
鈥�
2.0
1.0
MHz
Clock High Time
tHI
250
鈥�
ns
Clock Low Time
tLO
250
鈥�
ns
CS Fall To First Rising CLK
Edge
tSUCS
100
鈥�
ns
Data Input Setup Time
tSU
50
鈥�
ns
Data Input Hold Time
tHD
50
鈥�
ns
CLK Fall To Output Data Valid
tDO
鈥�
200
ns
CLK Fall To Output Enable
tEN
鈥�
200
ns
CS Rise To Output Disable
tDIS
鈥�
100
ns
CS Disable Time
tCSH
500
鈥�
ns
D
OUT Rise Time
tR
鈥�
100
ns
D
OUT Fall Time
tF
鈥�
100
ns
Power Requirements
Operating Voltage
VDD
2.7
鈥�
5.5
V
Operating Current
IDD
鈥�
320
225
400
鈥�
A
VDD=VREF = 5V, DOUT unloaded
VDD=VREF = 2.7V, DOUT unloaded
Standby Current
IDDS
鈥�0.5
2.0
A
CS = VDD = 5.0V
ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics:
Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, VREF = 5V,
TA = -40掳C to +85掳C,fSAMPLE = 100 ksps and fCLK = 20*fSAMPLE
Parameters
Sym
Min
Typ
Max
Units
Conditions
Note 1:
This parameter is established by characterization and not 100% tested.
2:
See graphs that relate linearity performance to VREF levels.
3:
Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity
performance, particularly at elevated temperatures. See Section 6.2 鈥淢aintaining Minimum Clock
Speed鈥�
, 鈥淢aintaining Minimum Clock Speed鈥�, for more information.
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