參數(shù)資料
型號： MCP3004T-I/ST
廠商： Microchip Technology
文件頁數(shù)： 34/40頁
文件大?。?/td> 0K
描述： IC ADC 10BIT 2.7V 4CH SPI14TSSOP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 10
采樣率（每秒）： 200k
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 14-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 14-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個單端，單極；2 個偽差分，單極
MCP3004/3008
DS21295D-page 4
2008 Microchip Technology Inc.
Leakage Current
—
0.001
±1
A
Switch Resistance
—
1000
—
Ω
Sample Capacitor
—
20
—
pF
Digital Input/Output
Data Coding Format
Straight Binary
High Level Input Voltage
VIH
0.7 VDD
——
V
Low Level Input Voltage
VIL
—
0.3 VDD
V
High Level Output Voltage
VOH
4.1
—
V
IOH = -1 mA, VDD = 4.5V
Low Level Output Voltage
VOL
——
0.4
V
IOL = 1 mA, VDD = 4.5V
Input Leakage Current
ILI
-10
—
10
A
VIN = VSS or VDD
Output Leakage Current
ILO
-10
—
10
A
VOUT = VSS or VDD
Pin Capacitance
(All Inputs/Outputs)
CIN,
COUT
——
10
pF
VDD = 5.0V (Note 1)
TA = 25°C, f = 1 MHz
Timing Parameters
Clock Frequency
fCLK
——
3.6
1.35
MHz
VDD = 5V (Note 3)
VDD = 2.7V (Note 3)
Clock High Time
tHI
125
—
ns
Clock Low Time
tLO
125
—
ns
CS Fall To First Rising CLK Edge
tSUCS
100
—
ns
CS Fall To Falling CLK Edge
tCSD
——
0
ns
Data Input Setup Time
tSU
50
—
ns
Data Input Hold Time
tHD
50
—
ns
CLK Fall To Output Data Valid
tDO
——
125
200
ns
VDD = 5V, See Figure 1-2
VDD = 2.7V, See Figure 1-2
CLK Fall To Output Enable
tEN
——
125
200
ns
VDD = 5V, See Figure 1-2
VDD = 2.7V, See Figure 1-2
CS Rise To Output Disable
tDIS
—
100
ns
See Test Circuits, Figure 1-2
CS Disable Time
tCSH
270
—
ns
D
OUT Rise Time
tR
—
100
ns
See Test Circuits, Figure 1-2
D
OUT Fall Time
tF
—
100
ns
See Test Circuits, Figure 1-2
ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics:
Unless otherwise noted, all parameters apply at VDD = 5V, VREF = 5V,
TA = -40°C to +85°C, fSAMPLE = 200 ksps and fCLK = 18*fSAMPLE. Unless otherwise noted, typical values apply for
VDD = 5V, TA = +25°C.
Parameter
Sym
Min
Typ
Max
Units
Conditions
Note 1:
This parameter is established by characterization and not 100% tested.
2:
See graphs that relate linearity performance to VREF levels.
3:
Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock
Speed”
, “Maintaining Minimum Clock Speed”, for more information.
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