MCM69R536
MCM69R618
6
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(0
°
C
≤
TA
≤
70
°
C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
(See Notes 1 through 4)
Parameter
Symbol
Min
Typical
–5
Typical
–6
Typical
–7
Typical
–8
Max
Unit
Notes
Core Power Supply Voltage
VDD
VDDQ
IDD1
3.15
—
—
—
—
3.6
V
Output Driver Supply Voltage
1.4
—
—
—
—
1.6
V
Active Power Supply Current
(x18)
(x36)
—
—
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
5
Quiescent Active Power Supply Current
(x18)
(x36)
IDD2
—
—
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
6, 10
Active Standby Power Supply Current
(x18)
(x36)
ISB1
—
—
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
7
Quiescent Standby Power Supply Current (x18)
(x36)
ISB2
—
—
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
8, 10
Sleep Mode Power Supply Current
ISB3
Vref (dc)
—
TBD
TBD
TBD
TBD
TBD
mA
9, 10
Input Reference DC Voltage
0.6
—
—
—
—
1.1
V
11
NOTES:
1. All data sheet parameters specified to full range of VDD unless otherwise noted. All voltages are referenced to voltage applied to VSS bumps.
2. Supply voltage applied to VDD connections.
3. Supply voltage applied to VDDQ connections.
4. All power supply currents measured with outputs open or deselected.
5. VDD = VDD (max), tKHKH = tKHKH (min), SS registered active, 50% read cycles.
6. VDD = VDD (max), tKHKH = dc, SS registered active.
7. VDD = VDD (max), tKHKH = tKHKH (min), SS registered inactive.
8. VDD = VDD (max), tKHKH = dc, SS registered inactive, ZZ low.
9. VDD = VDD (Max), tKHKH = dc, registered inactive, ZZ high.
10. 200 mV
≥
Vin
≥
VDDQ – 200 mV.
11. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of Vref is supported, the peak to peak ac component
superimposed on Vref may not exceed 5% of the dc component of Vref.
DC INPUT CHARACTERISTICS
Parameter
Symbol
Min
Max
Unit
Notes
DC Input Logic High
VIH (dc)
VIL (dc)
Ilkg
Vin
VDIF (dc)
VCM (dc)
VX
Vref + 0.1
– 0.3
VDD + 0.3
Vref – 0.1
±
5
V
DC Input Logic Low (See Figure 2)
V
1
Input Leakage Current
—
μ
A
2
Clock Input Signal Voltage
– 0.3
VDD + 0.3
VDD + 0.6
1.1
V
Clock Input Differential Voltage
0.2
V
3
Clock Input Common Mode Voltage Range (See Figure 3)
0.68
V
4
Clock Input Crossing Point Voltage Range (See Figure 3)
0.68
1.1
V
NOTES:
1. Inputs may undershoot to –0.5 V (peak) for up to 20% tKHKH (e.g., 2 ns at a clock cycle time of 10 ns).
2. 0 V
≤
Vin
≤
VDDQ for all pins.
3. Minimum differential input voltage required for differential input clock operation.
4. Maximum rejectable common mode input voltage variation.