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參數(shù)資料
| 型號(hào)： | MCM69R536 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 1M Synchronous Late Write Fast SRAM(1M位同步遲寫、快速靜態(tài)RAM) |
| 中文描述： | 100萬同步后寫入快速靜態(tài)存儲(chǔ)器（100萬位同步遲寫，快速靜態(tài)內(nèi)存） |
| 文件頁(yè)數(shù)： | 16/20頁(yè) |
| 文件大?。?/td> | 141K |
| 代理商： | MCM69R536 |
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MCM69R536
MCM69R618
16
MOTOROLA FAST SRAM
MCM69R536 Bump/Bit Scan Order
BIT
No.
Signal
Name
Bump
ID
Bit
No.
Signal
Name
Bump
ID
1
M2
5R
36
NC
3B
2
SA
4P
37
NC
2B
3
SA
4T
38
SA
3A
4
SA
6R
39
SA
3C
5
SA
5T
40
SA
2C
6
ZZ
7T
41
SA
2A
7
DQa
6P
42
DQc
2D
8
DQa
7P
43
DQc
1D
9
DQa
6N
44
DQc
2E
10
DQa
7N
45
DQc
1E
11
DQa
6M
46
DQc
2F
12
DQa
6L
47
DQc
2G
13
DQa
7L
48
DQc
1G
14
DQa
6K
49
DQc
2H
15
DQa
7K
50
DQc
1H
16
SBa
5L
51
SBc
3G
17
CK
4L
52
ZQ
4D
18
CK
4K
53
SS
4E
19
G
4F
54
NF
4G
20
SBb
5G
55
NF
4H
21
DQb
7H
56
SW
4M
22
DQb
6H
57
SBd
3L
23
DQb
7G
58
DQd
1K
24
DQb
6G
59
DQd
2K
25
DQb
6F
60
DQd
1L
26
DQb
7E
61
DQd
2L
27
DQb
6E
62
DQd
2M
28
DQb
7D
63
DQd
1N
29
DQb
6D
64
DQd
2N
30
SA
6A
65
DQd
1P
31
SA
6C
66
DQd
2P
32
SA
5C
67
SA
3T
33
SA
5A
68
SA
2R
34
NC
6B
69
SA
4N
35
NC
5B
70
M1
3R
MCM69R618 Bump/Bit Scan Order
Bit
No.
Signal
Name
Bump
ID
Bit
No.
Signal
Name
Bump
ID
1
M2
5R
36
SBb
3G
2
SA
6T
37
ZQ
4D
3
SA
4P
38
SS
4E
4
SA
6R
39
NF
4G
5
SA
5T
40
NF
4H
6
ZZ
7T
41
SW
4M
7
DQa
7P
42
DQb
2K
8
DQa
6N
43
DQb
1L
9
DQa
6L
44
DQb
2M
10
DQa
7K
45
DQb
1N
11
SBa
5L
46
DQb
2P
12
CK
4L
47
SA
3T
13
CK
4K
48
SA
2R
14
G
4F
49
SA
4N
15
DQa
6H
50
SA
2T
16
DQa
7G
51
M1
3R
17
DQa
6F
18
DQa
7E
19
DQa
6D
20
SA
6A
21
SA
6C
22
SA
5C
23
SA
5A
24
NC
6B
25
NC
5B
26
NC
3B
27
NC
2B
28
SA
3A
29
SA
3C
30
SA
2C
31
SA
2A
32
DQb
1D
33
DQb
2E
34
DQb
2G
35
DQb
1H
NOTES:
1. The NC pads listed in this table are indeed no connects, but are represented in the boundary scan register by a “place holder” bit that is forced
to logic 1. These pads are reserved for use as address inputs on higher density RAMs that follow this pad out and scan order standard.
2. In scan mode, differential inputs CK and CK are referenced to each other and must be at opposite logic levels for reliable operation.
3. ZQ, M1, and M2 are not ordinary inputs and may not respond to standard I/O logic levels. ZQ, M1, and M2 must be driven to within 100 mV
of a VDD or VSS supply rail to ensure consistent results.
4. ZZ must remain at VIL during boundary scan to ensure consistent results.
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