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參數(shù)資料
| 型號： | MCM63P818ZP66 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | SRAM |
| 英文描述： | 256K X 18 CACHE SRAM, 7 ns, PBGA119 |
| 封裝： | 7 X 17 MM, PLASTIC, BGA-119 |
| 文件頁數(shù)： | 10/21頁 |
| 文件大?。?/td> | 451K |
| 代理商： | MCM63P818ZP66 |
MCM63P736
MCM63P818
18
MOTOROLA FAST SRAM
APPLICATION INFORMATION
SLEEP MODE
A sleep mode feature, the ZZ pin, has been implemented
on the MCM63P736 and MCM63P818. It allows the system
designer to place the RAM in the lowest possible power
condition by asserting ZZ. The sleep mode timing diagram
shows the different modes of operation: Normal Operation,
No READ/WRITE Allowed, and Sleep Mode. Each mode has
its own set of constraints and conditions that are allowed.
Normal Operation: All inputs must meet setup and hold
times prior to sleep and tZZREC nanoseconds after re-
covering from sleep. Clock (K) must also meet cycle, high,
and low times during these periods. Two cycles prior to
sleep, initiation of either a read or write operation is not
allowed.
No READ/WRITE: During the period of time just prior to
sleep and during recovery from sleep, the assertion of either
ADSC, ADSP, or any write signal is not allowed. If a write
operation occurs during these periods, the memory array
may be corrupted. Validity of data out from the RAM can not
be guaranteed immediately after ZZ is asserted (prior to
being in sleep).
Sleep Mode: The RAM automatically deselects itself. The
RAM disconnects its internal clock buffer. The external clock
may continue to run without impacting the RAMs sleep
current (IZZ). All inputs are allowed to toggle — the RAM will
not be selected and perform any reads or writes. However, if
inputs toggle, the IZZ (max) specification will not be met.
Note: It is invalid to go from stop clock mode directly into
sleep mode.
NON–BURST SYNCHRONOUS OPERATION
Although this BurstRAM has been designed for PowerPC–
and other high end MPU–based systems, these SRAMs can
be used in other high speed L2 cache or memory applica-
tions that do not require the burst address feature. Most L2
caches designed with a synchronous interface can make use
of the MCM63P736 and MCM63P818. The burst counter
feature of the BurstRAMs can be disabled, and the SRAMs
can be configured to act upon a continuous stream of ad-
dresses. See Figure 6.
CONTROL PIN TIE VALUES EXAMPLE (H
≥ VIH, L ≤ VIL)
Non–Burst
ADSP
ADSC
ADV
SE1
SE2
LBO
Sync Non–Burst,
Pipelined SRAM
H
L
H
L
H
X
NOTE: Although X is specified in the table as a don’t care, the pin
must be tied either high or low.
WRITES
READS
DQ
K
Q(B)
Q(A)
ADDR
A
B
CD
EF
GH
W
Q(D)
Q(C)
D(F)
D(E)
D(H)
D(G)
G
Figure 6. Example Configuration as Non–Burst Synchronous SRAM
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For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCM63P818ZP66R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| MCM63P837 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:256K x 36 and 512K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| MCM63R836 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCM63R836 |
| MCM63R836A | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:8M Late Write HSTL |
| MCM63R836FC3.0 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCM63R836 |
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