參數(shù)資料
型號(hào)： MCM63P818ZP66
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： SRAM
英文描述： 256K X 18 CACHE SRAM, 7 ns, PBGA119
封裝： 7 X 17 MM, PLASTIC, BGA-119
文件頁(yè)數(shù)： 1/21頁(yè)
文件大?。?/td> 451K
代理商： MCM63P818ZP66
MCM63P736
MCM63P818
1
MOTOROLA FAST SRAM
128K x 36 and 256K x 18 Bit
Pipelined BurstRAM
Synchronous Fast Static RAM
The MCM63P736 and MCM63P818 are 4M–bit synchronous fast static RAMs
designed to provide a burstable, high performance, secondary cache for the
PowerPC
and other high performance microprocessors. The MCM63P736 is
organized as 128K words of 36 bits each, and the MCM63P818 is organized as
256K words of 18 bits each. These devices integrate input registers, an output
register, a 2–bit address counter, and high speed SRAM onto a single monolithic
circuit for reduced parts count in cache data RAM applications. Synchronous
design allows precise cycle control with the use of an external clock (K).
Addresses (SA), data inputs (DQx), and all control signals except output
enable (G), sleep mode (ZZ), and linear burst order (LBO) are clock (K) controlled
through positive–edge–triggered noninverting registers.
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
addresses can be generated internally by the MCM63P736 and MCM63P818
(burst sequence operates in linear or interleaved mode dependent upon the state
of LBO) and controlled by the burst address advance (ADV) input pin.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-
nous write enable (SW) are provided to allow writes to either individual bytes or
to all bytes. The bytes are designated as “a”, “b”, etc. SBa controls DQa, SBb
controls DQb, etc. Individual bytes are written if the selected byte writes SBx are
asserted with SW. All bytes are written if either SGW is asserted or if all SBx and
SW are asserted.
For read cycles, pipelined SRAMs output data is temporarily stored by an
edge–triggered output register and then released to the output buffers at the next
rising edge of clock (K).
The MCM63P736 and MCM63P818 operate from a 3.3 V core power supply
and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and outputs
are JEDEC standard JESD8–5 compatible.
MCM63P736/MCM63P818–133 = 4 ns Access/7.5 ns Cycle (133 MHz)
MCM63P736/MCM63P818–100 = 5 ns Access/10 ns Cycle (100 MHz)
MCM63P736/MCM63P818–66 = 7 ns Access/15 ns Cycle (66 MHz)
3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply
ADSP, ADSC, and ADV Burst Control Pins
Selectable Burst Sequencing Order (Linear/Interleaved)
Two–Cycle Deselect Timing
Internally Self–Timed Write Cycle
Byte Write and Global Write Control
Sleep Mode (ZZ)
JEDEC Standard 100–Pin TQFP and 119–Pin PBGA Packages
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
Order this document
by MCM63P736/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MCM63P736
MCM63P818
ZP PACKAGE
PBGA
CASE 999–02
TQ PACKAGE
TQFP
CASE 983A–01
REV 3
3/12/99
Motorola, Inc. 1999
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MCM63P818ZP66R 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P837 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:256K x 36 and 512K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63R836 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCM63R836
MCM63R836A 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:8M Late Write HSTL
MCM63R836FC3.0 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCM63R836
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