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參數(shù)資料
| 型號： | MCM20014IBB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | 1/3” Color VGA Digital Image Sensor |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CQCC48 |
| 封裝： | CERAMIC, LCC-48 |
| 文件頁數(shù)： | 8/54頁 |
| 文件大?。?/td> | 761K |
| 代理商： | MCM20014IBB |
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MOTOROLA
MCM20014
8
The Integration Time for CFCM is defined by a combi-
nation of the width of the virtual frame and the integra-
tion time register, (
Table 38 on page 38
and
Table 39 on
page 39
); and can be expressed as:
Integration Time = (cint
d
+ 1) * T
row
where cint
d
is the number of virtual frame row times de-
sired for integration time. Therefore, the integration time
in CFCM mode can be adjusted in steps of virtual frame
row times. This equation for Integration Time is valid
only for T
row
> T
lim
. For virtual frames where T
row
< T
lim
,
the integration time is different for the first cint
d
rows
and is defined as:
Integration Time
cintdrows
= T
fc
+ (cint
d
* T
row
)
By using the default values in the Virtual Frame defini-
tion and Integration Time registers, an 00
h
loaded into
the Internal Timing Control Register, and assuming a
standard video square pixel clock rate of 13.5Mhz, we
can calculate the frame rate and integration time as:
Row Time = (749 + 16 + 16 + 19) / 13.5e6 = 59.26
μ
s
Frame Time = (524 + 1) * 59.26
μ
s = 31.11ms which re-
sults in a Frame Rate of 32.21 frames per second.
Integration Time = (524 + 1) * 59.26
μ
s = 31.26ms.
2.1.8 SFCM Integration Time Control
The Integration Time for the SFCM is defined by the in-
tegration time register (
Table 37 on page 38
through
Ta-
ble 39 on page 39
) and can be expressed as:
Integration Time = sint
d
* 16 * MCLK
period
where sint
d
is a number. Therefore, the user can adjust
integration time in steps of 16 MCLK periods.
2.2 Analog Signal Processing Chain Overview
The MCM20014
’
s analog signal processing (ASP)
chain incorporates Correlated Double Sampling (CDS),
Frame Rate Clamp (FRC), two Digitally Programmable
Gain Amplifiers (DPGA), Offset Correction (DOVA), and
a 10-bit Analog to Digital Converter (ADC).
2.2.1 Correlated Double Sampling (CDS)
The uncertainty associated with the reset action of a ca-
pacitive node results in a reset noise which is equal to
kTC; C being the capacitance of the node, T the temper-
ature and k the Boltzmann constant. A common way of
eliminating this noise source in all image sensors is to
use Correlated Double Sampling. The output signal is
sampled twice, once for its reset (reference) level and
once for the actual video signal. These values are sam-
pled and held while a difference amplifier subtracts the
reference level from the signal output. Double sampling
of the signal eliminates correlated noise sources.
Figure 9. Conceptual block diagram of CDS
implementation.
2.2.2 Frame Rate Clamp (FRC)
The FRC (
Figure 10
) is designed to provide a feed for-
ward dark level subtract reference level measurement.
In the automatic FRC mode, the optical black level ref-
erence is re-established each time the image sensor
begins a new frame. The MCM20014 uses optical black
(dark) pixels to aid in establishing this reference.
Figure 10. FRC Conceptual Block Diagram
On the MCM20014, dark pixel input signals should be
sampled for a minimum of 137
μ
s to allow the two 0.1
μ
F
capacitors at the CLRCA and CLRCB pins sufficient
time to charge for 10-bit accuracy. This guarantees that
the FRC
’
s
“
droop
”
will be maintained at <750
μ
V
,
thus
assuring the specified ADC 10-bit accuracy at +0.5
LSB. Therefore, at maximum operational frequency
(13.5 MHz), the imager would require 6 frames to estab-
lish the dark pixel reference for subsequent active pixel
processing. The dark pixel sample period is automati-
cally controlled internally and it is set to skip the first 2
dark rows and then sample the next dark row. When
AMP
S/H1
S/H2
CDSP1
CDSP2
AVIN
V+
V-
+
-
V+
V-
BUF
1X
FRC
V
cm
CLRCA
V
cm
Cap
LRCA
0.1
μ
LRCLMP
LRCLMP
+
BUF
-
1X
CLRCB
Cap
LRCB
0.1
μ
LRCLMP
LRCLMP
Previous
+
-
LRCLMP
V
cm
LRCLMP
Stage
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