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參數(shù)資料
| 型號： | MCK12140DG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 1/5頁 |
| 文件大小： | 0K |
| 描述： | IC DETECTOR PHASE-FREQ 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 98 |
| 類型： | 相頻探測器 |
| PLL： | 無 |
| 輸入： | ECL |
| 輸出： | ECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 800MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 4.75 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOICN |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1115 (CN2011-ZH PDF) |
| 其它名稱： | MCK12140DGOS |
Semiconductor Components Industries, LLC, 2006
July, 2006 Rev. 9
1
Publication Order Number:
MCH12140/D
MCH12140, MCK12140
Phase-Frequency Detector
Description
The MCH/K12140 is a phase frequencydetector intended for
phaselocked loop applications which require a minimum amount of
phase and frequency difference at lock. When used in conjunction
with high performance VCO such as the MC100EL1648, a high
bandwidth PLL can be realized. The device is functionally compatible
with the MC12040 phasefrequency detector with the maximum
frequency extending to 800 MHz.
When the Reference (R) and VCO (V) inputs are unequal in
frequency and/or phase, the differential UP (U) and DOWN (D)
outputs will provide pulse streams which when subtracted and
integrated provide an error voltage for control of a VCO. See
AND8040 for further information. The device is packaged in a small
outline, surface mount 8lead SOIC package. There are two versions
of the device to provide I/O compatibility to the two existing ECL
standards. The MCH12140 is compatible with MECL 10H
logic
levels while the MCK12140 is compatible to 100 K ECL logic levels.
This device can also be used in +5.0 V systems. See AND8020 for
termination information
Features
800 MHz Typical Bandwidth
Small Outline 8-Lead SOIC Package
75 kW Internal Input Pulldown Resistors
>1000 V ESD Protection
PbFree Packages are Available
For proper operation, the input edge rate of the R and V inputs
should be less than 5.0 ns.
Figure 1. Logic Diagram
SQ
R
RQ
V
U (fR > fV)
D (fV > fR)
S
SOIC8
D SUFFIX
CASE 751
PIN CONNECTIONS
MARKING
DIAGRAM
x
= H or K
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
VCC
8
U
D
R
V
VEE
7
6
5
1
2
3
4
(Top View)
http://onsemi.com
x140
ALYW
G
1
8
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
1
8
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