參數(shù)資料
型號: MCIMX356AJM5B
廠商: Freescale Semiconductor
文件頁數(shù): 75/147頁
文件大?。?/td> 0K
描述: IC MPU IMX35 ARM11 400MAPBGA
標(biāo)準(zhǔn)包裝: 90
系列: i.MX35
核心處理器: ARM11
芯體尺寸: 32-位
速度: 532MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,MMC,SPI,SSI,UART/USART,USB OTG
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 96
程序存儲器類型: ROMless
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.33 V ~ 1.47 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 400-LFBGA
包裝: 托盤
i.MX35 Applications Processors for Automotive Products, Rev. 10
Freescale Semiconductor
33
4.9.4
Embedded Trace Macrocell (ETM) Electrical Specifications
ETM is an ARM protocol. The timing specifications in this section are given as a guide for a test point
access (TPA) that supports TRACECLK frequencies up to 133 MHz.
Figure 9 depicts the TRACECLK timings of ETM, and Table 30 lists the timing parameters.
Figure 9. ETM TRACECLK Timing Diagram
Figure 10 depicts the setup and hold requirements of the trace data pins with respect to TRACECLK, and
Table 31 lists the timing parameters.
Figure 10. Trace Data Timing Diagram
4.9.4.1
Half-Rate Clocking Mode
When half-rate clocking is used, the trace data signals are sampled by the TPA on both the rising and falling
edges of TRACECLK, where TRACECLK is half the frequency of the clock shown in Figure 10. The same
Ts and Th parameters from Table 31 still apply with respect to the falling edge of the TRACECLK signal.
Table 30. ETM TRACECLK Timing Parameters
ID
Parameter
Min.
Max.
Unit
Tcyc
Clock period
Frequency dependent
ns
Twl
Low pulse width
2
ns
Twh
High pulse width
2
ns
Tr
Clock and data rise time
3
ns
Tf
Clock and data fall time
3
ns
Table 31. ETM Trace Data Timing Parameters
ID
Parameter
Min.
Max.
Unit
Ts
Data setup
2
ns
Th
Data hold
1
ns
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