i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
113
Figure 90. SRCK Timing
Figure 91. STCLK Timing
4.9.22
SSI Electrical Specifications
This section describes electrical characteristics of the SSI.
NOTE
All of the timing for the SSI is given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables
and in the figures.
All timing is on AUDMUX signals when SSI is being used for data
transfer.
“Tx” and “Rx” refer to the transmit and receive sections of the SSI,
respectively.
For internal frame sync operations using the external clock, the FS
timing will be the same as that of Tx Data (for example, during AC97
mode of operation).
SRCK
(Output)
VM
srckp
srckph
srckpl
STCLK
(Input)
VM
stclkp
stclkph
stclkpl