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參數(shù)資料
| 型號(hào)： | MCIMX31LDVMN5DR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 24/118頁 |
| 文件大小： | 0K |
| 描述： | IC MPU I.MX31L CONSUMR 473MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 系列： | i.MX31 |
| 核心處理器： | ARM11 |
| 芯體尺寸： | 32-位 |
| 速度： | 532MHz |
| 連通性： | 1 線，ATA，EBI/EMI，F(xiàn)IR，I²C，MMC/SD，PCMCIA，SIM，SPI，SSI，UART/USART，USB，USB OTG |
| 外圍設(shè)備： | DMA，LCD，POR，PWM，WDT |
| 程序存儲(chǔ)器類型： | ROMless |
| RAM 容量： | 16K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.22 V ~ 3.3 V |
| 振蕩器型： | 外部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 473-LFBGA |
| 包裝： | 帶卷 (TR) |
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Electrical Characteristics
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
13
Table 8 provides the operating ranges.
NOTE
The term NVCC in this section refers to the associated supply rail of an
input or output. The association is shown in the Signal Multiplexing chapter
of the reference manual.
CAUTION
NVCC6 and NVCC9 must be at the same voltage potential. These supplies
are connected together on-chip to optimize ESD damage immunity.
Table 8. Operating Ranges
Symbol
Parameter
Min
Max
Units
QVCC,
QVCC1,
QVCC4
Core Operating Voltage1,2,3
1 Measured at package balls, including peripherals, ARM, and L2 cache supplies (QVCC, QVCC1, QVCC4, respectively).
2 The core voltage must be higher than 1.38V to avoid corrupted data during transfers from the USB HS. Please refer to Errata
file ENGcm02610 ID.
3
If the Core voltage is supplied by the MC13738, it will be 1.6 ± 0.05 V during the power-up sequence and this is allowed. After
power-up the voltage should be reduced to avoid operation in overdrive mode.
V
0
≤ fARM ≤ 400 MHz, non-overdrive
0
≤ fARM ≤ 532 MHz, non-overdrive
0
≤ fARM ≤ 532 MHz, overdrive4
4 Supply voltage is considered “overdrive” for voltages above 1.52 V. Operation time in overdrive—whether switching or
not—must be limited to a cumulative duration of 1.25 years (10,950 hours) or less to sustain the maximum operating voltage
without significant device degradation—for example, 25% (average 6 hours out of 24 yours per day) duty cycle for 5-year rated
equipment. To tolerate the maximum operating overdrive voltage for 10 years, the device must have a duty cycle of 12.5% or
less in overdrive (for example 3 out of 24 hours per day). Below 1.52 V, duty cycle restrictions may apply for equipment rated
above 5 years.
1.22
1.38
1.52
1.47
1.52
1.65
State Retention Voltage5
5 The SR voltage is applied to QVCC, QVCC1, and QVCC4 after the device is placed in SR mode. The Real-Time Clock (RTC)
is operational in State Retention (SR) mode.
0.95
—
NVCC1,
NVCC3–10
I/O Supply Voltage, except DDR6non-overdrive
overdrive7
6 Overshoot and undershoot conditions (transitions above NVCC and below GND) on I/O must be held below 0.6 V, and the
duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must be
controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other
methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.
1.75
>3.1
3.1
3.3
V
NVCC2,
NVCC21,
NVCC22
I/O Supply Voltage, DDR only
1.75
1.95
V
FVCC, MVCC,
SVCC, UVCC
PLL (Phase-Locked Loop) and FPM (Frequency Pre-multiplier) Supply Voltage8
non-overdrive
overdrive4
1.3
>1.47
1.47
1.6
V
IOQVDD
On-device Level Shifter Supply Voltage
1.6
1.9
V
FUSE_VDD
Fusebox read Supply Voltage9, 10
1.65
1.95
V
Fusebox write (program) Supply Voltage11
3.0
3.3
V
TA
Operating Ambient Temperature Range12
–20
70
oC
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