i.MX27 and i.MX27L Data Sheet, Rev. 1.8
70
Freescale Semiconductor
Electrical Characteristics
NOTE
High is defined as 80% of signal value and low is defined as 20% of signal
value. All timings are listed according to this NFC clock frequency
(multiples of NFC clock period) except NF16, which is not NFC clock
related.
The read data is generated by the NAND Flash device and sampled with the
internal NFC clock.
NF6
NFALE Setup Time
tALS
T
—
45
—
30
—
ns
NF7
NFALE Hold Time
tALH
T
—
45
—
30
—
ns
NF8
Data Setup Time
tDS
T
—
45
—
30
—
ns
NF9
Data Hold Time
tDH
T
—
45
—
30
—
ns
NF10
Write Cycle Time
tWC
2T
—
90
—
60
—
ns
NF11
NFWE Hold Time
tWH
T
—
45
—
30
—
ns
NF12
Ready to NFRE Low
tRR
4T
—
180
—
120
—
ns
NF13
NFRE Pulse Width
tRP
1.5T
—
67.5
—
45
—
ns
NF14
READ Cycle Time
tRC
2T
—
90
—
60
—
ns
NF15
NFRE High Hold Time
tREH
0.5T
—
22.5
—
15
—
ns
NF16
Data Setup on READ
tDSR
15
—
15
—
15
—
ns
NF17
Data Hold on READ
tDHR
0
—
0
—
0
—
ns
Table 35. NFC Target Timing Parameters (continued)
ID
Parameter
Symbol
Relationship to NFC
clock period (T)
NFC clock 22.17 MHz
T = 45 ns
NFC clock 33.25 MHz
T = 30 ns
Unit
Min
Max
Min
Max
Min
Max
