參數(shù)資料
型號(hào): MCIMX27LMOP4AR2
廠商: Freescale Semiconductor
文件頁數(shù): 130/152頁
文件大小: 0K
描述: IC MPU I.MX27 IN 19X19 473MAPBGA
標(biāo)準(zhǔn)包裝: 750
系列: i.MX27
核心處理器: ARM9
芯體尺寸: 32-位
速度: 400MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,MMC,智能卡,SPI,SSI,UART/USART,USB OTG
外圍設(shè)備: DMA,LCD,POR,PWM,WDT
程序存儲(chǔ)器類型: ROMless
RAM 容量: 45K x 8
電壓 - 電源 (Vcc/Vdd): 1.38 V ~ 1.52 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 473-LFBGA
包裝: 帶卷 (TR)
i.MX27 and i.MX27L Data Sheet, Rev. 1.8
Freescale Semiconductor
79
Electrical Characteristics
Figure 41. Mobile DDR SDRAM Write Cycle Timing Diagram
NOTE
SDRAM CLK and DQS related parameters are being measured from the
50% point—that is, high is defined as 50% of signal value and low is
defined as 50% of signal value.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is, Table 41 indicates SDRAM requirements. All output signals
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
Table 41. Mobile DDR SDRAM Write Cycle Timing Parameters1
1 Test condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703.
ID
Parameter
Symbol
Min
Max
Unit
SD17
DQ and DQM setup time to DQS
tDS
0.95
ns
SD18
DQ and DQM hold time to DQS
tDH
0.95
ns
SD19
Write cycle DQS falling edge to SDCLK output delay time.
tDSS
1.8
ns
SD20
Write cycle DQS falling edge to SDCLK output hold time.
tDSH
1.8
ns
Note:
SDCLK
DQS (output)
DQ (output)
DQM (output)
Data
DM
SD17
SD18
SD19
SD20
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