參數(shù)資料
型號(hào): MCIMX258CVM4
廠商: Freescale Semiconductor
文件頁數(shù): 28/153頁
文件大小: 0K
描述: IC MPU I.MX25 IND 400MAPBGA
標(biāo)準(zhǔn)包裝: 90
系列: i.MX25
核心處理器: ARM9
芯體尺寸: 32-位
速度: 400MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,MMC,智能卡,SPI,SSI,UART/USART,USB OTG
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 128
程序存儲(chǔ)器類型: 外部程序存儲(chǔ)器
RAM 容量: 144K x 8
電壓 - 電源 (Vcc/Vdd): 1.15 V ~ 1.52 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 3x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 400-LFBGA
包裝: 托盤
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor
123
Table 97 shows the timing specifications for USB in VP_VM unidirectional mode.
3.7.20.2
USB Parallel Interface Timing
Table 98 defines the USB parallel interface signals.
Table 97. USB Timing Specifications in VP_VM Unidirectional Mode
No.
Parameter
Signal
Direction
Min.
Max.
Unit
Conditions/
Reference Signal
US30
Tx rise/fall time
USB_DAT_VP
Out
5.0
ns
50 pF
US31
Tx rise/fall time
USB_SE0_VM
Out
5.0
ns
50 pF
US32
Tx rise/fall time
USB_TXOE_B
Out
5.0
ns
50 pF
US33
Tx duty cycle
USB_DAT_VP
Out
49.0
51.0
%
US34
Tx high overlap
USB_SE0_VM
Out
0.0
ns
USB_DAT_VP
US35
Tx low overlap
USB_SE0_VM
Out
0.0
ns
USB_DAT_VP
US36
Enable delay
USB_DAT_VP
USB_SE0_VM
In
8.0
ns
USB_TXOE_B
US37
Disable delay
USB_DAT_VP
USB_SE0_VM
In
10.0
ns
USB_TXOE_B
US38
Rx rise/fall time
USB_VP1
In
3.0
ns
35 pF
US39
Rx rise/fall time
USB_VM1
In
3.0
ns
35 pF
US40
Rx skew
USB_VP1
Out
–4.0
+4.0
ns
USB_SE0_VM
US41
Rx skew
USB_RCV
Out
–6.0
+2.0
ns
USB_DAT_VP
Table 98. Signal Definitions for USB Parallel Interface
Name
Direction
Signal Description
USB_Clk
In
Interface clock—All interface signals are synchronous to USB_Clk
USB_Data[7:0]
I/O
Bidirectional data bus, driven low by the link during idle—Bus ownership is determined by the
direction
USB_Dir
In
Direction—Control the direction of the data bus
USB_Stp
Out
Stop—The link asserts this signal for one clock cycle to stop the data stream currently on the bus
USB_Nxt
In
Next—The PHY asserts this signal to throttle the data
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