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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | MCIMX257CJN4A |
| 寤犲晢锛� | Freescale Semiconductor |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 16/153闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MPU I.MX25 AUTO 347MAPBGA |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 189 |
| 绯诲垪锛� | i.MX25 |
| 鏍稿績铏曠悊鍣細 | ARM9 |
| 鑺珨灏哄锛� | 32-浣� |
| 閫熷害锛� | 400MHz |
| 閫ｉ€氭€э細 | 1 绶�锛孋AN锛孍BI/EMI锛屼互澶恫(w菐ng)锛孖²C锛孧MC锛屾櫤鑳藉崱锛孲PI锛孲SI锛孶ART/USART锛孶SB OTG |
| 澶栧湇瑷�(sh猫)鍌欙細 | DMA锛孖²S锛孡CD锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 128 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ(l猫i)鍨嬶細 | 澶栭儴绋嬪簭瀛樺劜(ch菙)鍣� |
| RAM 瀹归噺锛� | 144K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 1.15 V ~ 1.52 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 3x12b |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 347-LFBGA |
| 鍖呰锛� | 鎵樼洡(p谩n) |
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i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
112
Freescale Semiconductor
assertion of soc is detected. Thus, if the soc signal is continuously asserted, the ADC undergoes successive
conversion cycles and achieves the maximum sampling rate. If soc is negated, no conversion is initiated.
Figure 82. Start-up Sequence
The output data can be read from adcout11...adcout0, and is available tdata nanoseconds after the rising
edge of eoc. The reset signal and the digital signals controlling the analog switches (ypsw, xpsw, ynsw,
xnsw) are totally asynchronous.
The following conditions are necessary to guarantee the correct operation of the ADC:
The input multiplexer selection (selin11鈥elin0) is stable during both the last clock cycle (14th)
and the first clock cycle (1st). The best way to guarantee this is to make the input multiplexer
selection during clock cycles 2 to 13.
The references are stable during clock cycle 1 to 13. The best way to guarantee this is to make the
reference multiplexer selection (selrefp and selrefn) before issuing an soc pulse and changing it
only after an eoc pulse has been acquired, during the last clock cycle (14).
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MCIMX257CVM4 | 鍔熻兘鎻忚堪:铏曠悊鍣� - 灏�(zhu膩n)闁€(m茅n)鎳�(y墨ng)鐢� SENNA IMX25 INDUST RoHS:鍚� 鍒堕€犲晢:Freescale Semiconductor 椤�(l猫i)鍨�:Multimedia Applications 鏍稿績:ARM Cortex A9 铏曠悊鍣ㄧ郴鍒�:i.MX6 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:1 GHz 鎸囦护/鏁�(sh霉)鎿�(j霉)绶╁瓨: 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鏁�(sh霉)鎿�(j霉) ROM 澶у皬: 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�:+ 95 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:MAPBGA-432 |
| MCIMX257DJM4 | 鍔熻兘鎻忚堪:铏曠悊鍣� - 灏�(zhu膩n)闁€(m茅n)鎳�(y墨ng)鐢� SENNA IMX25 COMM RoHS:鍚� 鍒堕€犲晢:Freescale Semiconductor 椤�(l猫i)鍨�:Multimedia Applications 鏍稿績:ARM Cortex A9 铏曠悊鍣ㄧ郴鍒�:i.MX6 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:1 GHz 鎸囦护/鏁�(sh霉)鎿�(j霉)绶╁瓨: 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鏁�(sh霉)鎿�(j霉) ROM 澶у皬: 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�:+ 95 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:MAPBGA-432 |
| MCIMX257DJM4A | 鍔熻兘鎻忚堪:铏曠悊鍣� - 灏�(zhu膩n)闁€(m茅n)鎳�(y墨ng)鐢� IMX25 1.2 COMM RoHS:鍚� 鍒堕€犲晢:Freescale Semiconductor 椤�(l猫i)鍨�:Multimedia Applications 鏍稿績:ARM Cortex A9 铏曠悊鍣ㄧ郴鍒�:i.MX6 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:1 GHz 鎸囦护/鏁�(sh霉)鎿�(j霉)绶╁瓨: 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鏁�(sh霉)鎿�(j霉) ROM 澶у皬: 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�:+ 95 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:MAPBGA-432 |
| MCIMX257DJM4AR2 | 鍒堕€犲晢:Freescale Semiconductor 鍔熻兘鎻忚堪:APPLICATIONS PROCESSOR 400-PIN MA-BGA T/R - Tape and Reel |
| MCIMX257DVM4 | 鍔熻兘鎻忚堪:IC MPU I.MX25 COMM 400MAPBGA RoHS:鏄� 椤�(l猫i)鍒�:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - 寰帶鍒跺櫒锛� 绯诲垪:i.MX25 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:260 绯诲垪:73S12xx 鏍稿績铏曠悊鍣�:80515 鑺珨灏哄:8-浣� 閫熷害:24MHz 閫ｉ€氭€�:I²C锛屾櫤鑳藉崱锛孶ART/USART锛孶SB 澶栧湇瑷�(sh猫)鍌�:LED锛孭OR锛學DT 杓稿叆/杓稿嚭鏁�(sh霉):9 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲�:64KB锛�64K x 8锛� 绋嬪簭瀛樺劜(ch菙)鍣ㄩ(l猫i)鍨�:闁冨瓨 EEPROM 澶у皬:- RAM 瀹归噺:2K x 8 闆诲 - 闆绘簮 (Vcc/Vdd):2.7 V ~ 5.5 V 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒:- 鎸暕鍣ㄥ瀷:鍏�(n猫i)閮� 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:68-VFQFN 瑁搁湶鐒婄洡(p谩n) 鍖呰:绠′欢 |
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