參數(shù)資料
型號: MCHRC705KJ1CDWE
廠商: Freescale Semiconductor
文件頁數(shù): 73/108頁
文件大小: 0K
描述: IC MCU 8BIT 64 BYTES RAM 16-S0IC
標準包裝: 47
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 4MHz
外圍設備: POR,WDT
輸入/輸出數(shù): 10
程序存儲器容量: 1.2KB(1.2K x 8)
程序存儲器類型: OTP
RAM 容量: 64 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
包裝: 管件
Port B
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
67
7.3.2 Data Direction Register B
Data direction register B determines whether each port B pin is an input or an output.
DDRB[3:2] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears DDRB[3:2], configuring all port B pins
as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 7-8 shows the I/O logic of port B.
Figure 7-8. Port B I/O Circuitry
Writing a logic 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0
disables the output buffer.
When bit DDRBx is a logic 1, reading address $0001 reads the PBx data latch. When bit DDRBx is a
logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 7-2 summarizes the operation of the port B pins.
Address:
$0005
Bit 7
654321
Bit 0
Read:
0
See Notes
DDRB3
DDRB2
See Note
Write:
Reset:
00000000
= Unimplemented
Note:
DDRB5, DDRB4, DDRB1, and DDRB0 should be configured as inputs at all times. These
bits are available for read/write but are not available externally. Configuring them as inputs
will ensure that the pulldown devices are enabled, thus properly terminating them.
Figure 7-7. Data Direction Register B (DDRB)
READ DDRB
WRITE DDRB
RESET
WRITE PORTB
READ PORTB
PBx
INTERNAL
D
AT
A
B
U
S
DDRBx
PBx
PDRBx
SWPDI
100-
A
PULLDOWN
WRITE PDRB
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