參數(shù)資料
型號: MCHLC705KJ1CDWE
廠商: Freescale Semiconductor
文件頁數(shù): 29/108頁
文件大?。?/td> 0K
描述: IC MCU 8BIT 64 BYTES RAM 16-SOIC
標準包裝: 47
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 10
程序存儲器容量: 1.2KB(1.2K x 8)
程序存儲器類型: OTP
RAM 容量: 64 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
包裝: 管件
Mask Option Register
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
27
2.8 Mask Option Register
The mask option register (MOR) is an EPROM/OTPROM byte that controls the following options:
COP watchdog (enable or disable)
External interrupt pin triggering (edge-sensitive only or edge- and level-sensitive)
Port A external interrupts (enable or disable)
Port pulldown resistors (enable or disable)
STOP instruction (stop mode or halt mode)
Crystal oscillator internal resistor (enable or disable)
EPROM security (enable or disable)
Short oscillator delay (enable or disable)
Take the following steps to program the mask option register (MOR):
1.
Apply the programming voltage, VPP, to the IRQ/VPP pin.
2.
Write to the MOR.
3.
Set the MPGM bit and wait for a time, tMPGM.
4.
Clear the MPGM bit.
5.
Reset the MCU.
SOSCD — Short Oscillator Delay Bit
The SOSCD bit controls the oscillator stabilization counter. The normal stabilization delay following
reset or exit from stop mode is 4064 tcyc. Setting SOSCD enables a 128 tcyc stabilization delay.
1 = Short oscillator delay enabled
0 = Short oscillator delay disabled
EPMSEC — EPROM Security Bit
The EPMSEC bit controls access to the EPROM/OTPROM.
1 = External access to EPROM/OTPROM denied
0 = External access to EPROM/OTPROM not denied
OSCRES — Oscillator Internal Resistor Bit
The OSCRES bit enables a 2-M
internal resistor in the oscillator circuit.
1 = Oscillator internal resistor enabled
0 = Oscillator internal resistor disabled
NOTE
Program the OSCRES bit to logic 0 in devices using low-speed crystal or
RC oscillators with external resistor.
Address:
$07F1
Bit 7
654321
Bit 0
Read:
SOSCD
EPMSEC
OSCRES
SWAIT
SWPDI
PIRQ
LEVEL
COPEN
Write:
Reset:
Unaffected by reset
Figure 2-4. Mask Option Register (MOR)
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