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| 型號： | MCF54417CMJ250 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, PBGA256 |
| 封裝： | 12 X 12 MM, ROHS COMPLAINT, MAPBGA-256 |
| 文件頁數(shù)： | 41/60頁 |
| 文件大?。?/td> | 1107K |
| 代理商： | MCF54417CMJ250 |
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MCF5441x ColdFire Microprocessor Data Sheet, Rev. 6
Preliminary—Subject to Change Without Notice
Electrical characteristics
Freescale Semiconductor
46
Figure 27. I2C input/output timings
4.22
Ethernet assembly timing specifications
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing
specs/constraints for the physical interface.
All Ethernet signals use pad type pad_fsr. The following timing specifications assume a pad slew rate setting of 11 and a load
of 50 pF.1
Table 30. I2C output timing specifications between SCL and SDA
Num
Characteristic
Min
Max
Units
I11
1 Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum
frequency (IFDR = 0x20) results in minimum output timings as shown in Table 30. The I2C interface is
designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual
position is affected by the prescale and division values programmed into the IFDR. However, the numbers
given in Table 30 are minimum values.
Start condition hold time
6
—
1/fSYS
I21
Clock low period
10
—
1/fSYS
I32
2 Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive
low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and
pull-up resistor values.
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH =2.4 V)
—
s
I41
Data hold time
7
—
1/fSYS
I53
3 Specified at a nominal 50-pF load.
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
—
3
ns
I61
Clock high time
10
—
1/fSYS
I71
Data setup time
2
—
1/fSYS
I81
Start condition setup time (for repeated start condition only)
20
—
1/fSYS
I91
Stop condition setup time
10
—
1/fSYS
1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting
(11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to
increase edge rise and fall times, thus reducing EMI.
I2
I6
I1
I4
I7
I8
I9
I5
I3
I2C_SCL
I2C_SDA
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCF54417CMJ250 | 制造商:Freescale Semiconductor 功能描述:IC 32-BIT MPU COLDFIRE 250MHZ 256-MA |
| MCF54418CMJ250 | 功能描述:微處理器 - MPU COLDFIREV4M CORE C90LP RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MCF54418CMJ250 | 制造商:Freescale Semiconductor 功能描述:IC 32-BIT MPU COLDFIRE 250MHZ 256-MA |
| MCF5441X | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCF5441x ColdFire Microprocessor Data Sheet |
| MCF54450 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ColdFire㈢ Microprocessor |
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