參數(shù)資料
型號: MCF54417CMJ250
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: MICROPROCESSOR, PBGA256
封裝: 12 X 12 MM, ROHS COMPLAINT, MAPBGA-256
文件頁數(shù): 36/60頁
文件大?。?/td> 1107K
代理商: MCF54417CMJ250
Electrical characteristics
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 6
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
41
Figure 24. SmartCard interface power-down AC timing
4.17
SSI timing specifications
This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given
for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync
(SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings
remain valid by inverting the clock signal (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the figures below.
All SSI signals use pad type pad_msr. The following timing specifications assume a pad slew rate setting of 11 and a load of 50
pF. When the SSI_MCLK output is not used, the maximum SSI bit clock (SSI_BCLK) frequency is such that timing can also
be met at slew rate settings 10 and 01.1
Table 23. Timing requirements for power-down sequence
Num
Description
Symbol
Min
Max
Unit
1
SIM reset to SIM clock stop
Srst2clk
0.9
f
CKIL
0.8
s
2
SIM reset to SIM TX data low
Srst2dat
1.8
f
CKIL
1.2
s
3
SIM reset to SIM voltage enable low
Srst2ven
2.7
f
CKIL
1.8
s
4
SIM presence detect to SIM reset low
Spd2rst
0.9
f
CKIL
25
ns
1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting
(11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to
increase edge rise and fall times, thus reducing EMI.
SIM_PD
SIM_RST
SIM_CLK
SIM__TX
SIM_VEN
Srst2clk
Srst2dat
Srst2ven
Spd2rst
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相關代理商/技術參數(shù)
參數(shù)描述
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