參數(shù)資料
型號: MCF54416CMJ250
廠商: Freescale Semiconductor
文件頁數(shù): 28/61頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 256MAPBGA
標準包裝: 450
系列: MCF5441x
核心處理器: Coldfire V4
芯體尺寸: 32-位
速度: 250MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,智能卡,SPI,SSI,UART/USART,USB,USB OTG
外圍設備: DMA,PWM,WDT
輸入/輸出數(shù): 87
程序存儲器類型: ROMless
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 1.14 V ~ 1.32 V
數(shù)據(jù)轉換器: A/D 8x12b,D/A 2x12b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 256-LBGA
包裝: 托盤
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Electrical characteristics
Freescale Semiconductor
34
Figure 16. Read data latch timing
4.12
DDR SDRAM controller timing specifications
The following timing numbers must be followed to properly latch or drive data onto the SDRAM memory bus. All timing
numbers are relative to the DQS byte lanes.
Table 18. SDRAM timing specifications
Num
Characteristic
Symbol
Min
Max
Unit
Notes
Frequency of operation
100
250
MHz
DD1
Clock period
tSDCK
4.0
10.0
ns
DD2
Pulse width high
tSDCKH
0.45
0.55
tSDCK
1
1 Pulse width high plus pulse width low cannot exceed min and max clock period.
DD3
Pulse width low
tSDCKL
0.45
0.55
tSDCK
3
DD4
Address, SD_CKE, SD_CAS, SD_RAS,
SD_WE, SD_CS[1:0] — output valid
tCMV
—0.5
t
SDCK + 1
ns
2
2 Command output valid should be 1/2 the memory bus clock (t
SDCK) plus some minor adjustments for process, temperature,
and voltage variations.
DD5
Address, SD_CKE, SD_CAS, SD_RAS,
SD_WE, SD_CS[1:0] — output hold
tCMH
0.5
t
SDCK – 1
ns
DD6
Write command to first DQS latching transition
tDQSS
—WL + 0.2
t
SDCK
ns
DD7
Data and data mask output setup (DQ
DQS)
relative to DQS (DDR write mode)
tQS
0.4
ns
3
4
DD8
Data and data mask output hold (DQS
DQ)
relative to DQS (DDR write mode)
tQH
0.4
ns
5
DD9
Input data skew relative to DQS (input setup)
tIS
—0.5
ns
6
DD10 Input data hold relative to DQS.
tIH
0.375
t
SDCK
—ns
7
NFC_R/B
NF13
NFC_CE
NFC_RE
NFC_IO[15:0]
Data from NF
NF5
NF15
NF16
NF10
NF14
NF17
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